1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _UAPI__RK_PCIE_EP_H__ 7*4882a593Smuzhiyun #define _UAPI__RK_PCIE_EP_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/types.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* rkep device mode status definition */ 12*4882a593Smuzhiyun #define RKEP_MODE_BOOTROM 1 13*4882a593Smuzhiyun #define RKEP_MODE_LOADER 2 14*4882a593Smuzhiyun #define RKEP_MODE_KERNEL 3 15*4882a593Smuzhiyun #define RKEP_MODE_FUN0 4 16*4882a593Smuzhiyun /* Common status */ 17*4882a593Smuzhiyun #define RKEP_SMODE_INIT 0 18*4882a593Smuzhiyun #define RKEP_SMODE_LNKRDY 1 19*4882a593Smuzhiyun #define RKEP_SMODE_LNKUP 2 20*4882a593Smuzhiyun #define RKEP_SMODE_ERR 0xff 21*4882a593Smuzhiyun /* Firmware download status */ 22*4882a593Smuzhiyun #define RKEP_SMODE_FWDLRDY 0x10 23*4882a593Smuzhiyun #define RKEP_SMODE_FWDLDONE 0x11 24*4882a593Smuzhiyun /* Application status*/ 25*4882a593Smuzhiyun #define RKEP_SMODE_APPRDY 0x20 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * rockchip pcie driver elbi ioctrl output data 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun struct pcie_ep_user_data { 31*4882a593Smuzhiyun __u64 bar0_phys_addr; 32*4882a593Smuzhiyun __u32 elbi_app_user[11]; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * rockchip driver cache ioctrl input param 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun struct pcie_ep_dma_cache_cfg { 39*4882a593Smuzhiyun __u64 addr; 40*4882a593Smuzhiyun __u32 size; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define PCIE_EP_OBJ_INFO_MAGIC 0x524B4550 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun enum pcie_ep_obj_irq_type { 46*4882a593Smuzhiyun OBJ_IRQ_UNKNOWN, 47*4882a593Smuzhiyun OBJ_IRQ_DMA, 48*4882a593Smuzhiyun OBJ_IRQ_USER, 49*4882a593Smuzhiyun OBJ_IRQ_ELBI, 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct pcie_ep_obj_irq_dma_status { 53*4882a593Smuzhiyun __u32 wr; 54*4882a593Smuzhiyun __u32 rd; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun enum pcie_ep_mmap_resource { 58*4882a593Smuzhiyun PCIE_EP_MMAP_RESOURCE_DBI, 59*4882a593Smuzhiyun PCIE_EP_MMAP_RESOURCE_BAR0, 60*4882a593Smuzhiyun PCIE_EP_MMAP_RESOURCE_BAR2, 61*4882a593Smuzhiyun PCIE_EP_MMAP_RESOURCE_BAR4, 62*4882a593Smuzhiyun PCIE_EP_MMAP_RESOURCE_MAX, 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* 66*4882a593Smuzhiyun * rockchip ep device information which is store in BAR0 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun struct pcie_ep_obj_info { 69*4882a593Smuzhiyun __u32 magic; 70*4882a593Smuzhiyun __u32 version; 71*4882a593Smuzhiyun struct { 72*4882a593Smuzhiyun __u16 mode; 73*4882a593Smuzhiyun __u16 submode; 74*4882a593Smuzhiyun } devmode; 75*4882a593Smuzhiyun __u8 reserved[0x1F4]; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun __u32 irq_type_rc; /* Generate in ep isr, valid only for rc, clear in rc */ 78*4882a593Smuzhiyun struct pcie_ep_obj_irq_dma_status dma_status_rc; /* Generate in ep isr, valid only for rc, clear in rc */ 79*4882a593Smuzhiyun __u32 irq_type_ep; /* Generate in ep isr, valid only for ep, clear in ep */ 80*4882a593Smuzhiyun struct pcie_ep_obj_irq_dma_status dma_status_ep; /* Generate in ep isr, valid only for ep, clear in ep */ 81*4882a593Smuzhiyun __u32 obj_irq_user_data; /* OBJ_IRQ_USER userspace data */ 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define PCIE_BASE 'P' 85*4882a593Smuzhiyun #define PCIE_DMA_GET_ELBI_DATA _IOR(PCIE_BASE, 0, struct pcie_ep_user_data) 86*4882a593Smuzhiyun #define PCIE_DMA_CACHE_INVALIDE _IOW(PCIE_BASE, 1, struct pcie_ep_dma_cache_cfg) 87*4882a593Smuzhiyun #define PCIE_DMA_CACHE_FLUSH _IOW(PCIE_BASE, 2, struct pcie_ep_dma_cache_cfg) 88*4882a593Smuzhiyun #define PCIE_DMA_IRQ_MASK_ALL _IOW(PCIE_BASE, 3, int) 89*4882a593Smuzhiyun #define PCIE_DMA_RAISE_MSI_OBJ_IRQ_USER _IOW(PCIE_BASE, 4, int) 90*4882a593Smuzhiyun #define PCIE_EP_GET_USER_INFO _IOR(PCIE_BASE, 5, struct pcie_ep_user_data) 91*4882a593Smuzhiyun #define PCIE_EP_SET_MMAP_RESOURCE _IOW(PCIE_BASE, 6, enum pcie_ep_mmap_resource) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif 94