1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef _UAPI__PCIE_DMA_TRX_H__ 6*4882a593Smuzhiyun #define _UAPI__PCIE_DMA_TRX_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/types.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun union pcie_dma_ioctl_param { 11*4882a593Smuzhiyun struct { 12*4882a593Smuzhiyun __u32 idx; 13*4882a593Smuzhiyun __u32 l_widx; 14*4882a593Smuzhiyun __u32 r_widx; 15*4882a593Smuzhiyun __u32 size; 16*4882a593Smuzhiyun __u32 chn; 17*4882a593Smuzhiyun } in; 18*4882a593Smuzhiyun struct { 19*4882a593Smuzhiyun __u32 lwa; 20*4882a593Smuzhiyun __u32 rwa; 21*4882a593Smuzhiyun } out; 22*4882a593Smuzhiyun __u32 lra; 23*4882a593Smuzhiyun __u32 count; 24*4882a593Smuzhiyun __u32 total_buffer_size; 25*4882a593Smuzhiyun __u64 local_addr; 26*4882a593Smuzhiyun __u32 buffer_size; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define PCIE_BASE 'P' 30*4882a593Smuzhiyun #define PCIE_DMA_START \ 31*4882a593Smuzhiyun _IOW(PCIE_BASE, 0, union pcie_dma_ioctl_param) 32*4882a593Smuzhiyun #define PCIE_DMA_GET_LOCAL_READ_BUFFER_INDEX \ 33*4882a593Smuzhiyun _IOR(PCIE_BASE, 1, union pcie_dma_ioctl_param) 34*4882a593Smuzhiyun #define PCIE_DMA_GET_LOCAL_REMOTE_WRITE_BUFFER_INDEX \ 35*4882a593Smuzhiyun _IOR(PCIE_BASE, 2, union pcie_dma_ioctl_param) 36*4882a593Smuzhiyun #define PCIE_DMA_FREE_LOCAL_READ_BUFFER_INDEX \ 37*4882a593Smuzhiyun _IOW(PCIE_BASE, 3, union pcie_dma_ioctl_param) 38*4882a593Smuzhiyun #define PCIE_DMA_SYNC_BUFFER_FOR_CPU \ 39*4882a593Smuzhiyun _IOW(PCIE_BASE, 4, union pcie_dma_ioctl_param) 40*4882a593Smuzhiyun #define PCIE_DMA_SYNC_BUFFER_TO_DEVICE \ 41*4882a593Smuzhiyun _IOW(PCIE_BASE, 5, union pcie_dma_ioctl_param) 42*4882a593Smuzhiyun #define PCIE_DMA_WAIT_TRANSFER_COMPLETE \ 43*4882a593Smuzhiyun _IO(PCIE_BASE, 6) 44*4882a593Smuzhiyun #define PCIE_DMA_SET_LOOP_COUNT \ 45*4882a593Smuzhiyun _IOW(PCIE_BASE, 7, union pcie_dma_ioctl_param) 46*4882a593Smuzhiyun #define PCIE_DMA_GET_TOTAL_BUFFER_SIZE \ 47*4882a593Smuzhiyun _IOR(PCIE_BASE, 8, union pcie_dma_ioctl_param) 48*4882a593Smuzhiyun #define PCIE_DMA_SET_BUFFER_SIZE \ 49*4882a593Smuzhiyun _IOW(PCIE_BASE, 9, union pcie_dma_ioctl_param) 50*4882a593Smuzhiyun #define PCIE_DMA_READ_FROM_REMOTE \ 51*4882a593Smuzhiyun _IOW(PCIE_BASE, 0xa, union pcie_dma_ioctl_param) 52*4882a593Smuzhiyun #define PCIE_DMA_USER_SET_BUF_ADDR \ 53*4882a593Smuzhiyun _IOW(PCIE_BASE, 0xb, union pcie_dma_ioctl_param) 54*4882a593Smuzhiyun #define PCIE_DMA_GET_BUFFER_SIZE \ 55*4882a593Smuzhiyun _IOR(PCIE_BASE, 0xc, union pcie_dma_ioctl_param) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #endif 58