1 /* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) */ 2 /* 3 * Rockchip module information 4 * Copyright (C) 2018-2019 Rockchip Electronics Co., Ltd. 5 */ 6 7 #ifndef _UAPI_RKMODULE_CAMERA_H 8 #define _UAPI_RKMODULE_CAMERA_H 9 10 #include <linux/types.h> 11 #include <linux/rk-video-format.h> 12 13 #define RKMODULE_API_VERSION KERNEL_VERSION(0, 1, 0x2) 14 15 /* using for rk3588 dual isp unite */ 16 #define RKMOUDLE_UNITE_EXTEND_PIXEL 128 17 /* using for rv1109 and rv1126 */ 18 #define RKMODULE_EXTEND_LINE 24 19 20 #define RKMODULE_NAME_LEN 32 21 #define RKMODULE_LSCDATA_LEN 289 22 23 #define RKMODULE_MAX_VC_CH 4 24 25 #define RKMODULE_PADF_GAINMAP_LEN 1024 26 #define RKMODULE_PDAF_DCCMAP_LEN 256 27 #define RKMODULE_AF_OTP_MAX_LEN 3 28 29 #define RKMODULE_MAX_SENSOR_NUM 8 30 31 #define RKMODULE_CAMERA_MODULE_INDEX "rockchip,camera-module-index" 32 #define RKMODULE_CAMERA_MODULE_FACING "rockchip,camera-module-facing" 33 #define RKMODULE_CAMERA_MODULE_NAME "rockchip,camera-module-name" 34 #define RKMODULE_CAMERA_LENS_NAME "rockchip,camera-module-lens-name" 35 36 #define RKMODULE_CAMERA_SYNC_MODE "rockchip,camera-module-sync-mode" 37 #define RKMODULE_INTERNAL_MASTER_MODE "internal_master" 38 #define RKMODULE_EXTERNAL_MASTER_MODE "external_master" 39 #define RKMODULE_SLAVE_MODE "slave" 40 41 /* BT.656 & BT.1120 multi channel 42 * On which channels it can send video data 43 * related with struct rkmodule_bt656_mbus_info 44 */ 45 #define RKMODULE_CAMERA_BT656_ID_EN_BITS_1 (0x1) 46 #define RKMODULE_CAMERA_BT656_ID_EN_BITS_2 (0x3) 47 #define RKMODULE_CAMERA_BT656_ID_EN_BITS_3 (0x7) 48 #define RKMODULE_CAMERA_BT656_ID_EN_BITS_4 (0xf) 49 #define RKMODULE_CAMERA_BT656_PARSE_ID_LSB BIT(0) 50 #define RKMODULE_CAMERA_BT656_PARSE_ID_MSB BIT(1) 51 #define RKMODULE_CAMERA_BT656_CHANNEL_0 BIT(2) 52 #define RKMODULE_CAMERA_BT656_CHANNEL_1 BIT(3) 53 #define RKMODULE_CAMERA_BT656_CHANNEL_2 BIT(4) 54 #define RKMODULE_CAMERA_BT656_CHANNEL_3 BIT(5) 55 #define RKMODULE_CAMERA_BT656_CHANNELS (RKMODULE_CAMERA_BT656_CHANNEL_0 | \ 56 RKMODULE_CAMERA_BT656_CHANNEL_1 | \ 57 RKMODULE_CAMERA_BT656_CHANNEL_2 | \ 58 RKMODULE_CAMERA_BT656_CHANNEL_3) 59 60 #define DPHY_MAX_LANE 4 61 #define RKMODULE_MULTI_DEV_NUM 4 62 63 #define RKMODULE_GET_MODULE_INFO \ 64 _IOR('V', BASE_VIDIOC_PRIVATE + 0, struct rkmodule_inf) 65 66 #define RKMODULE_AWB_CFG \ 67 _IOW('V', BASE_VIDIOC_PRIVATE + 1, struct rkmodule_awb_cfg) 68 69 #define RKMODULE_AF_CFG \ 70 _IOW('V', BASE_VIDIOC_PRIVATE + 2, struct rkmodule_af_cfg) 71 72 #define RKMODULE_LSC_CFG \ 73 _IOW('V', BASE_VIDIOC_PRIVATE + 3, struct rkmodule_lsc_cfg) 74 75 #define RKMODULE_GET_HDR_CFG \ 76 _IOR('V', BASE_VIDIOC_PRIVATE + 4, struct rkmodule_hdr_cfg) 77 78 #define RKMODULE_SET_HDR_CFG \ 79 _IOW('V', BASE_VIDIOC_PRIVATE + 5, struct rkmodule_hdr_cfg) 80 81 #define RKMODULE_SET_CONVERSION_GAIN \ 82 _IOW('V', BASE_VIDIOC_PRIVATE + 6, __u32) 83 84 #define RKMODULE_GET_LVDS_CFG \ 85 _IOR('V', BASE_VIDIOC_PRIVATE + 7, struct rkmodule_lvds_cfg) 86 87 #define RKMODULE_SET_DPCC_CFG \ 88 _IOW('V', BASE_VIDIOC_PRIVATE + 8, struct rkmodule_dpcc_cfg) 89 90 #define RKMODULE_GET_NR_SWITCH_THRESHOLD \ 91 _IOR('V', BASE_VIDIOC_PRIVATE + 9, struct rkmodule_nr_switch_threshold) 92 93 #define RKMODULE_SET_QUICK_STREAM \ 94 _IOW('V', BASE_VIDIOC_PRIVATE + 10, __u32) 95 96 #define RKMODULE_GET_BT656_INTF_TYPE \ 97 _IOR('V', BASE_VIDIOC_PRIVATE + 11, __u32) 98 99 #define RKMODULE_GET_VC_FMT_INFO \ 100 _IOR('V', BASE_VIDIOC_PRIVATE + 12, struct rkmodule_vc_fmt_info) 101 102 #define RKMODULE_GET_VC_HOTPLUG_INFO \ 103 _IOR('V', BASE_VIDIOC_PRIVATE + 13, struct rkmodule_vc_hotplug_info) 104 105 #define RKMODULE_GET_START_STREAM_SEQ \ 106 _IOR('V', BASE_VIDIOC_PRIVATE + 14, __u32) 107 108 #define RKMODULE_GET_VICAP_RST_INFO \ 109 _IOR('V', BASE_VIDIOC_PRIVATE + 15, struct rkmodule_vicap_reset_info) 110 111 #define RKMODULE_SET_VICAP_RST_INFO \ 112 _IOW('V', BASE_VIDIOC_PRIVATE + 16, struct rkmodule_vicap_reset_info) 113 114 #define RKMODULE_GET_BT656_MBUS_INFO \ 115 _IOR('V', BASE_VIDIOC_PRIVATE + 17, struct rkmodule_bt656_mbus_info) 116 117 #define RKMODULE_GET_DCG_RATIO \ 118 _IOR('V', BASE_VIDIOC_PRIVATE + 18, struct rkmodule_dcg_ratio) 119 120 #define RKMODULE_GET_SONY_BRL \ 121 _IOR('V', BASE_VIDIOC_PRIVATE + 19, __u32) 122 123 #define RKMODULE_GET_CHANNEL_INFO \ 124 _IOWR('V', BASE_VIDIOC_PRIVATE + 20, struct rkmodule_channel_info) 125 126 #define RKMODULE_GET_SYNC_MODE \ 127 _IOR('V', BASE_VIDIOC_PRIVATE + 21, __u32) 128 129 #define RKMODULE_SET_SYNC_MODE \ 130 _IOW('V', BASE_VIDIOC_PRIVATE + 22, __u32) 131 132 #define RKMODULE_SET_MCLK \ 133 _IOW('V', BASE_VIDIOC_PRIVATE + 23, struct rkmodule_mclk_data) 134 135 #define RKMODULE_SET_LINK_FREQ \ 136 _IOW('V', BASE_VIDIOC_PRIVATE + 24, __s64) 137 138 #define RKMODULE_SET_BUS_CONFIG \ 139 _IOW('V', BASE_VIDIOC_PRIVATE + 25, struct rkmodule_bus_config) 140 141 #define RKMODULE_GET_BUS_CONFIG \ 142 _IOR('V', BASE_VIDIOC_PRIVATE + 26, struct rkmodule_bus_config) 143 144 #define RKMODULE_SET_REGISTER \ 145 _IOW('V', BASE_VIDIOC_PRIVATE + 27, struct rkmodule_reg) 146 147 #define RKMODULE_SYNC_I2CDEV \ 148 _IOW('V', BASE_VIDIOC_PRIVATE + 28, __u8) 149 150 #define RKMODULE_SYNC_I2CDEV_COMPLETE \ 151 _IOW('V', BASE_VIDIOC_PRIVATE + 29, __u8) 152 153 #define RKMODULE_SET_DEV_INFO \ 154 _IOW('V', BASE_VIDIOC_PRIVATE + 30, struct rkmodule_dev_info) 155 156 #define RKMODULE_SET_CSI_DPHY_PARAM \ 157 _IOW('V', BASE_VIDIOC_PRIVATE + 31, struct rkmodule_csi_dphy_param) 158 159 #define RKMODULE_GET_CSI_DPHY_PARAM \ 160 _IOWR('V', BASE_VIDIOC_PRIVATE + 32, struct rkmodule_csi_dphy_param) 161 162 #define RKMODULE_GET_CSI_DSI_INFO \ 163 _IOWR('V', BASE_VIDIOC_PRIVATE + 33, __u32) 164 165 #define RKMODULE_GET_HDMI_MODE \ 166 _IOR('V', BASE_VIDIOC_PRIVATE + 34, __u32) 167 168 #define RKMODULE_SET_SENSOR_INFOS \ 169 _IOWR('V', BASE_VIDIOC_PRIVATE + 35, struct rkmodule_sensor_infos) 170 171 #define RKMODULE_GET_READOUT_LINE_CNT_PER_LINE \ 172 _IOR('V', BASE_VIDIOC_PRIVATE + 36, __u32) 173 174 #define RKMODULE_GET_GROUP_ID \ 175 _IOR('V', BASE_VIDIOC_PRIVATE + 37, __u32) 176 177 #define RKMODULE_SET_GROUP_ID \ 178 _IOW('V', BASE_VIDIOC_PRIVATE + 38, __u32) 179 180 #define RKMODULE_GET_CAPTURE_MODE \ 181 _IOR('V', BASE_VIDIOC_PRIVATE + 39, struct rkmodule_capture_info) 182 183 #define RKMODULE_SET_CAPTURE_MODE \ 184 _IOW('V', BASE_VIDIOC_PRIVATE + 40, struct rkmodule_capture_info) 185 186 struct rkmodule_i2cdev_info { 187 __u8 slave_addr; 188 } __attribute__ ((packed)); 189 190 struct rkmodule_dev_info { 191 union { 192 struct rkmodule_i2cdev_info i2c_dev; 193 __u32 reserved[8]; 194 }; 195 } __attribute__ ((packed)); 196 197 /* csi0/csi1 phy support full/split mode */ 198 enum rkmodule_phy_mode { 199 PHY_FULL_MODE, 200 PHY_SPLIT_01, 201 PHY_SPLIT_23, 202 }; 203 204 struct rkmodule_mipi_lvds_bus { 205 __u32 bus_type; 206 __u32 lanes; 207 __u32 phy_mode; /* data type enum rkmodule_phy_mode */ 208 }; 209 210 struct rkmodule_bus_config { 211 union { 212 struct rkmodule_mipi_lvds_bus bus; 213 __u32 reserved[32]; 214 }; 215 } __attribute__ ((packed)); 216 217 struct rkmodule_reg { 218 __u64 num_regs; 219 __u64 preg_addr; 220 __u64 preg_value; 221 __u64 preg_addr_bytes; 222 __u64 preg_value_bytes; 223 } __attribute__ ((packed)); 224 225 /** 226 * struct rkmodule_base_inf - module base information 227 * 228 */ 229 struct rkmodule_base_inf { 230 char sensor[RKMODULE_NAME_LEN]; 231 char module[RKMODULE_NAME_LEN]; 232 char lens[RKMODULE_NAME_LEN]; 233 } __attribute__ ((packed)); 234 235 /** 236 * struct rkmodule_fac_inf - module factory information 237 * 238 */ 239 struct rkmodule_fac_inf { 240 __u32 flag; 241 242 char module[RKMODULE_NAME_LEN]; 243 char lens[RKMODULE_NAME_LEN]; 244 __u32 year; 245 __u32 month; 246 __u32 day; 247 } __attribute__ ((packed)); 248 249 /** 250 * struct rkmodule_awb_inf - module awb information 251 * 252 */ 253 struct rkmodule_awb_inf { 254 __u32 flag; 255 256 __u32 r_value; 257 __u32 b_value; 258 __u32 gr_value; 259 __u32 gb_value; 260 261 __u32 golden_r_value; 262 __u32 golden_b_value; 263 __u32 golden_gr_value; 264 __u32 golden_gb_value; 265 } __attribute__ ((packed)); 266 267 /** 268 * struct rkmodule_lsc_inf - module lsc information 269 * 270 */ 271 struct rkmodule_lsc_inf { 272 __u32 flag; 273 274 __u16 lsc_w; 275 __u16 lsc_h; 276 __u16 decimal_bits; 277 278 __u16 lsc_r[RKMODULE_LSCDATA_LEN]; 279 __u16 lsc_b[RKMODULE_LSCDATA_LEN]; 280 __u16 lsc_gr[RKMODULE_LSCDATA_LEN]; 281 __u16 lsc_gb[RKMODULE_LSCDATA_LEN]; 282 283 __u16 width; 284 __u16 height; 285 __u16 table_size; 286 } __attribute__ ((packed)); 287 288 /** 289 * enum rkmodule_af_dir - enum of module af otp direction 290 */ 291 enum rkmodele_af_otp_dir { 292 AF_OTP_DIR_HORIZONTAL = 0, 293 AF_OTP_DIR_UP = 1, 294 AF_OTP_DIR_DOWN = 2, 295 }; 296 297 /** 298 * struct rkmodule_af_otp - module af otp in one direction 299 */ 300 struct rkmodule_af_otp { 301 __u32 vcm_start; 302 __u32 vcm_end; 303 __u32 vcm_dir; 304 }; 305 306 /** 307 * struct rkmodule_af_inf - module af information 308 * 309 */ 310 struct rkmodule_af_inf { 311 __u32 flag; 312 __u32 dir_cnt; 313 struct rkmodule_af_otp af_otp[RKMODULE_AF_OTP_MAX_LEN]; 314 } __attribute__ ((packed)); 315 316 /** 317 * struct rkmodule_pdaf_inf - module pdaf information 318 * 319 */ 320 struct rkmodule_pdaf_inf { 321 __u32 flag; 322 323 __u32 gainmap_width; 324 __u32 gainmap_height; 325 __u32 dccmap_width; 326 __u32 dccmap_height; 327 __u32 dcc_mode; 328 __u32 dcc_dir; 329 __u16 gainmap[RKMODULE_PADF_GAINMAP_LEN]; 330 __u16 dccmap[RKMODULE_PDAF_DCCMAP_LEN]; 331 } __attribute__ ((packed)); 332 333 /** 334 * struct rkmodule_otp_module_inf - otp module info 335 * 336 */ 337 struct rkmodule_otp_module_inf { 338 __u32 flag; 339 __u8 vendor[8]; 340 __u32 module_id; 341 __u16 version; 342 __u16 full_width; 343 __u16 full_height; 344 __u8 supplier_id; 345 __u8 year; 346 __u8 mouth; 347 __u8 day; 348 __u8 sensor_id; 349 __u8 lens_id; 350 __u8 vcm_id; 351 __u8 drv_id; 352 __u8 flip; 353 } __attribute__ ((packed)); 354 355 /** 356 * struct rkmodule_inf - module information 357 * 358 */ 359 struct rkmodule_inf { 360 struct rkmodule_base_inf base; 361 struct rkmodule_fac_inf fac; 362 struct rkmodule_awb_inf awb; 363 struct rkmodule_lsc_inf lsc; 364 struct rkmodule_af_inf af; 365 struct rkmodule_pdaf_inf pdaf; 366 struct rkmodule_otp_module_inf module_inf; 367 } __attribute__ ((packed)); 368 369 /** 370 * struct rkmodule_awb_inf - module awb information 371 * 372 */ 373 struct rkmodule_awb_cfg { 374 __u32 enable; 375 __u32 golden_r_value; 376 __u32 golden_b_value; 377 __u32 golden_gr_value; 378 __u32 golden_gb_value; 379 } __attribute__ ((packed)); 380 381 /** 382 * struct rkmodule_af_cfg 383 * 384 */ 385 struct rkmodule_af_cfg { 386 __u32 enable; 387 __u32 vcm_start; 388 __u32 vcm_end; 389 __u32 vcm_dir; 390 } __attribute__ ((packed)); 391 392 /** 393 * struct rkmodule_lsc_cfg 394 * 395 */ 396 struct rkmodule_lsc_cfg { 397 __u32 enable; 398 } __attribute__ ((packed)); 399 400 /** 401 * NO_HDR: linear mode 402 * HDR_X2: hdr two frame or line mode 403 * HDR_X3: hdr three or line mode 404 * HDR_COMPR: linearised and compressed data for hdr 405 */ 406 enum rkmodule_hdr_mode { 407 NO_HDR = 0, 408 HDR_X2 = 5, 409 HDR_X3 = 6, 410 HDR_COMPR, 411 }; 412 413 enum rkmodule_hdr_compr_segment { 414 HDR_COMPR_SEGMENT_4 = 4, 415 HDR_COMPR_SEGMENT_12 = 12, 416 HDR_COMPR_SEGMENT_16 = 16, 417 }; 418 419 /* rkmodule_hdr_compr 420 * linearised and compressed data for hdr: data_src = K * data_compr + XX 421 * 422 * bit: bit of src data, max 20 bit. 423 * segment: linear segment, support 4, 6 or 16. 424 * k_shift: left shift bit of slop amplification factor, 2^k_shift, [0 15]. 425 * slope_k: K * 2^k_shift. 426 * data_src_shitf: left shift bit of source data, data_src = 2^data_src_shitf 427 * data_compr: compressed data. 428 */ 429 struct rkmodule_hdr_compr { 430 enum rkmodule_hdr_compr_segment segment; 431 __u8 bit; 432 __u8 k_shift; 433 __u8 data_src_shitf[HDR_COMPR_SEGMENT_16]; 434 __u16 data_compr[HDR_COMPR_SEGMENT_16]; 435 __u32 slope_k[HDR_COMPR_SEGMENT_16]; 436 }; 437 438 /** 439 * HDR_NORMAL_VC: hdr frame with diff virtual channels 440 * HDR_LINE_CNT: hdr frame with line counter 441 * HDR_ID_CODE: hdr frame with identification code 442 */ 443 enum hdr_esp_mode { 444 HDR_NORMAL_VC = 0, 445 HDR_LINE_CNT, 446 HDR_ID_CODE, 447 }; 448 449 /* 450 * CSI/DSI input select IOCTL 451 */ 452 enum rkmodule_csi_dsi_seq { 453 RKMODULE_CSI_INPUT = 0, 454 RKMODULE_DSI_INPUT, 455 }; 456 457 /** 458 * lcnt: line counter 459 * padnum: the pixels of padding row 460 * padpix: the payload of padding 461 * idcd: identification code 462 * efpix: identification code of Effective line 463 * obpix: identification code of OB line 464 */ 465 struct rkmodule_hdr_esp { 466 enum hdr_esp_mode mode; 467 union { 468 struct { 469 __u32 padnum; 470 __u32 padpix; 471 } lcnt; 472 struct { 473 __u32 efpix; 474 __u32 obpix; 475 } idcd; 476 } val; 477 }; 478 479 struct rkmodule_hdr_cfg { 480 __u32 hdr_mode; 481 struct rkmodule_hdr_esp esp; 482 struct rkmodule_hdr_compr compr; 483 } __attribute__ ((packed)); 484 485 /* sensor lvds sync code 486 * sav: start of active video codes 487 * eav: end of active video codes 488 */ 489 struct rkmodule_sync_code { 490 __u16 sav; 491 __u16 eav; 492 }; 493 494 /* sensor lvds difference sync code mode 495 * LS_FIRST: valid line ls-le or sav-eav 496 * invalid line fs-fe or sav-eav 497 * FS_FIRST: valid line fs-le 498 * invalid line ls-fe 499 * ls: line start 500 * le: line end 501 * fs: frame start 502 * fe: frame end 503 * SONY_DOL_HDR_1: sony dol hdr pattern 1 504 * SONY_DOL_HDR_2: sony dol hdr pattern 2 505 */ 506 enum rkmodule_lvds_mode { 507 LS_FIRST = 0, 508 FS_FIRST, 509 SONY_DOL_HDR_1, 510 SONY_DOL_HDR_2 511 }; 512 513 /* sync code of different frame type (hdr or linear) for lvds 514 * act: valid line sync code 515 * blk: invalid line sync code 516 */ 517 struct rkmodule_lvds_frm_sync_code { 518 struct rkmodule_sync_code act; 519 struct rkmodule_sync_code blk; 520 }; 521 522 /* sync code for lvds of sensor 523 * odd_sync_code: sync code of odd frame id for lvds of sony sensor 524 * even_sync_code: sync code of even frame id for lvds of sony sensor 525 */ 526 struct rkmodule_lvds_frame_sync_code { 527 struct rkmodule_lvds_frm_sync_code odd_sync_code; 528 struct rkmodule_lvds_frm_sync_code even_sync_code; 529 }; 530 531 /* lvds sync code category of sensor for different operation */ 532 enum rkmodule_lvds_sync_code_group { 533 LVDS_CODE_GRP_LINEAR = 0x0, 534 LVDS_CODE_GRP_LONG, 535 LVDS_CODE_GRP_MEDIUM, 536 LVDS_CODE_GRP_SHORT, 537 LVDS_CODE_GRP_MAX 538 }; 539 540 /* struct rkmodule_lvds_cfg 541 * frm_sync_code[index]: 542 * index == LVDS_CODE_GRP_LONG: 543 * sync code for frame of linear mode or for long frame of hdr mode 544 * index == LVDS_CODE_GRP_MEDIUM: 545 * sync code for medium long frame of hdr mode 546 * index == LVDS_CODE_GRP_SHOR: 547 * sync code for short long frame of hdr mode 548 */ 549 struct rkmodule_lvds_cfg { 550 enum rkmodule_lvds_mode mode; 551 struct rkmodule_lvds_frame_sync_code frm_sync_code[LVDS_CODE_GRP_MAX]; 552 } __attribute__ ((packed)); 553 554 /** 555 * struct rkmodule_dpcc_cfg 556 * enable: 0 -> disable dpcc, 1 -> enable multiple, 557 * 2 -> enable single, 3 -> enable all; 558 * cur_single_dpcc: the strength of single dpcc; 559 * cur_multiple_dpcc: the strength of multiple dpcc; 560 * total_dpcc: the max strength; 561 */ 562 struct rkmodule_dpcc_cfg { 563 __u32 enable; 564 __u32 cur_single_dpcc; 565 __u32 cur_multiple_dpcc; 566 __u32 total_dpcc; 567 } __attribute__ ((packed)); 568 569 /** 570 * nr switch by gain 571 * direct: 0 -> up_thres LSNR to HSNR, 1 -> up_thres HSNR to LSNR 572 * up_thres: threshold of nr change from low gain to high gain 573 * down_thres: threshold of nr change from high gain to low gain; 574 * div_coeff: Coefficients converted from float to int 575 */ 576 struct rkmodule_nr_switch_threshold { 577 __u32 direct; 578 __u32 up_thres; 579 __u32 down_thres; 580 __u32 div_coeff; 581 } __attribute__ ((packed)); 582 583 /** 584 * enum rkmodule_bt656_intf_type 585 * to support sony bt656 raw 586 */ 587 enum rkmodule_bt656_intf_type { 588 BT656_STD_RAW = 0, 589 BT656_SONY_RAW, 590 }; 591 592 /** 593 * struct rkmodule_vc_fmt_info - virtual channels fmt info 594 * 595 */ 596 struct rkmodule_vc_fmt_info { 597 __u32 width[RKMODULE_MAX_VC_CH]; 598 __u32 height[RKMODULE_MAX_VC_CH]; 599 __u32 fps[RKMODULE_MAX_VC_CH]; 600 } __attribute__ ((packed)); 601 602 /** 603 * struct rkmodule_vc_hotplug_info - virtual channels hotplug status info 604 * detect_status: hotplug status 605 * bit 0~3 means channels id, value : 0 -> plug out, 1 -> plug in. 606 */ 607 struct rkmodule_vc_hotplug_info { 608 __u8 detect_status; 609 } __attribute__ ((packed)); 610 611 612 /* sensor start stream sequence 613 * RKMODULE_START_STREAM_DEFAULT: by default 614 * RKMODULE_START_STREAM_BEHIND : sensor start stream should be behind the controller 615 * RKMODULE_START_STREAM_FRONT : sensor start stream should be in front of the controller 616 */ 617 enum rkmodule_start_stream_seq { 618 RKMODULE_START_STREAM_DEFAULT = 0, 619 RKMODULE_START_STREAM_BEHIND, 620 RKMODULE_START_STREAM_FRONT, 621 }; 622 623 /* 624 * HDMI to MIPI-CSI MODE IOCTL 625 */ 626 enum rkmodule_hdmiin_mode_seq { 627 RKMODULE_HDMIIN_DEFAULT = 0, 628 RKMODULE_HDMIIN_MODE, 629 }; 630 /* 631 * the causation to do cif reset work 632 */ 633 enum rkmodule_reset_src { 634 RKCIF_RESET_SRC_NON = 0x0, 635 RKCIF_RESET_SRC_ERR_CSI2, 636 RKCIF_RESET_SRC_ERR_LVDS, 637 RKICF_RESET_SRC_ERR_CUTOFF, 638 RKCIF_RESET_SRC_ERR_HOTPLUG, 639 RKCIF_RESET_SRC_ERR_APP, 640 }; 641 642 struct rkmodule_vicap_reset_info { 643 __u32 is_reset; 644 enum rkmodule_reset_src src; 645 } __attribute__ ((packed)); 646 647 struct rkmodule_bt656_mbus_info { 648 __u32 flags; 649 __u32 id_en_bits; 650 } __attribute__ ((packed)); 651 652 /* DCG ratio (float) = integer + decimal / div_coeff */ 653 struct rkmodule_dcg_ratio { 654 __u32 integer; 655 __u32 decimal; 656 __u32 div_coeff; 657 }; 658 659 struct rkmodule_channel_info { 660 __u32 index; 661 __u32 vc; 662 __u32 width; 663 __u32 height; 664 __u32 bus_fmt; 665 __u32 data_type; 666 __u32 data_bit; 667 } __attribute__ ((packed)); 668 669 /* 670 * link to vicap 671 * linear mode: pad0~pad3 for id0~id3; 672 * 673 * HDR_X2: id0 fiexd to vc0 for long frame 674 * id1 fixed to vc1 for short frame; 675 * id2~id3 reserved, can config by PAD2~PAD3 676 * 677 * HDR_X3: id0 fiexd to vc0 for long frame 678 * id1 fixed to vc1 for middle frame 679 * id2 fixed to vc2 for short frame; 680 * id3 reserved, can config by PAD3 681 * 682 * link to isp, the connection relationship is as follows 683 */ 684 enum rkmodule_max_pad { 685 PAD0, /* link to isp */ 686 PAD1, /* link to csi wr0 | hdr x2:L x3:M */ 687 PAD2, /* link to csi wr1 | hdr x3:L */ 688 PAD3, /* link to csi wr2 | hdr x2:M x3:S */ 689 PAD_MAX, 690 }; 691 692 /* 693 * sensor exposure sync mode 694 */ 695 enum rkmodule_sync_mode { 696 NO_SYNC_MODE = 0, 697 EXTERNAL_MASTER_MODE, 698 INTERNAL_MASTER_MODE, 699 SLAVE_MODE, 700 }; 701 702 struct rkmodule_mclk_data { 703 __u32 enable; 704 __u32 mclk_index; 705 __u32 mclk_rate; 706 __u32 reserved[8]; 707 }; 708 709 /* 710 * csi dphy param 711 * lp_vol_ref -> Reference voltage-645mV for LP Function control pin 712 * for rk3588 dcphy 713 * 3'b000 : 605mV 714 * 3'b001 : 625mV 715 * 3'b010 : 635mV 716 * 3'b011 : 645mV 717 * 3'b100 : 655mV 718 * 3'b101 : 665mV 719 * 3'b110 : 685mV 720 * 3'b111 : 725mV 721 * 722 * lp_hys_sw -> LP-RX Hysteresis Level Control 723 * for rk3588 dcphy 724 * 2'b00=45mV 725 * 2'b01=65mV 726 * 2'b10=85mV 727 * 2'b11=100mV 728 * 729 * lp_escclk_pol_sel -> LP ESCCLK Polarity sel 730 * for rk3588 dcphy 731 * 1'b0: normal 732 * 1'b1: swap ,Increase 1ns delay 733 * 734 * skew_data_cal_clk -> Skew Calibration Manual Data Fine Delay Control Register 735 * for rk3588 dcphy 736 * BIT[4:0] 30ps a step 737 * 738 * clk_hs_term_sel/data_hs_term_sel -> HS-RX Termination Impedance Control 739 * for rk3588 dcphy 740 * 3b'000 : 102Ω 741 * 3b'001 : 99.1Ω 742 * 3b'010 : 96.6Ω (default) 743 * 3b'011 : 94.1Ω 744 * 3b'100 : 113Ω 745 * 3b'101 : 110Ω 746 * 3b'110 : 107Ω 747 * 3b'111 : 104Ω 748 */ 749 750 enum csi2_dphy_vendor { 751 PHY_VENDOR_INNO = 0x0, 752 PHY_VENDOR_SAMSUNG = 0x01, 753 }; 754 755 struct rkmodule_csi_dphy_param { 756 __u32 vendor; 757 __u32 lp_vol_ref; 758 __u32 lp_hys_sw[DPHY_MAX_LANE]; 759 __u32 lp_escclk_pol_sel[DPHY_MAX_LANE]; 760 __u32 skew_data_cal_clk[DPHY_MAX_LANE]; 761 __u32 clk_hs_term_sel; 762 __u32 data_hs_term_sel[DPHY_MAX_LANE]; 763 __u32 reserved[32]; 764 }; 765 766 struct rkmodule_sensor_fmt { 767 __u32 sensor_index; 768 __u32 sensor_width; 769 __u32 sensor_height; 770 }; 771 772 struct rkmodule_sensor_infos { 773 struct rkmodule_sensor_fmt sensor_fmt[RKMODULE_MAX_SENSOR_NUM]; 774 }; 775 776 enum rkmodule_capture_mode { 777 RKMODULE_CAPTURE_MODE_NONE = 0, 778 RKMODULE_MULTI_DEV_COMBINE_ONE, 779 RKMODULE_ONE_CH_TO_MULTI_ISP, 780 RKMODULE_MULTI_CH_TO_MULTI_ISP, 781 RKMODULE_MULTI_CH_COMBINE_SQUARE, 782 }; 783 784 struct rkmodule_multi_dev_info { 785 __u32 dev_idx[RKMODULE_MULTI_DEV_NUM]; 786 __u32 combine_idx[RKMODULE_MULTI_DEV_NUM]; 787 __u32 pixel_offset; 788 __u32 dev_num; 789 __u32 reserved[8]; 790 }; 791 792 struct rkmodule_one_to_multi_info { 793 __u32 isp_num; 794 __u32 frame_pattern[RKMODULE_MULTI_DEV_NUM]; 795 }; 796 797 struct rkmodule_multi_combine_info { 798 __u32 combine_num; 799 __u32 combine_index[RKMODULE_MULTI_DEV_NUM]; 800 }; 801 802 struct rkmodule_capture_info { 803 __u32 mode; 804 union { 805 struct rkmodule_multi_dev_info multi_dev; 806 struct rkmodule_one_to_multi_info one_to_multi; 807 struct rkmodule_multi_combine_info multi_combine_info; 808 }; 809 }; 810 811 #endif /* _UAPI_RKMODULE_CAMERA_H */ 812