1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * omap3isp.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * TI OMAP3 ISP - User-space API 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2010 Nokia Corporation 8*4882a593Smuzhiyun * Copyright (C) 2009 Texas Instruments, Inc. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 11*4882a593Smuzhiyun * Sakari Ailus <sakari.ailus@iki.fi> 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 14*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 15*4882a593Smuzhiyun * published by the Free Software Foundation. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but 18*4882a593Smuzhiyun * WITHOUT ANY WARRANTY; without even the implied warranty of 19*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 20*4882a593Smuzhiyun * General Public License for more details. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License 23*4882a593Smuzhiyun * along with this program; if not, write to the Free Software 24*4882a593Smuzhiyun * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 25*4882a593Smuzhiyun * 02110-1301 USA 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #ifndef OMAP3_ISP_USER_H 29*4882a593Smuzhiyun #define OMAP3_ISP_USER_H 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #include <linux/types.h> 32*4882a593Smuzhiyun #include <linux/videodev2.h> 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* 35*4882a593Smuzhiyun * Private IOCTLs 36*4882a593Smuzhiyun * 37*4882a593Smuzhiyun * VIDIOC_OMAP3ISP_CCDC_CFG: Set CCDC configuration 38*4882a593Smuzhiyun * VIDIOC_OMAP3ISP_PRV_CFG: Set preview engine configuration 39*4882a593Smuzhiyun * VIDIOC_OMAP3ISP_AEWB_CFG: Set AEWB module configuration 40*4882a593Smuzhiyun * VIDIOC_OMAP3ISP_HIST_CFG: Set histogram module configuration 41*4882a593Smuzhiyun * VIDIOC_OMAP3ISP_AF_CFG: Set auto-focus module configuration 42*4882a593Smuzhiyun * VIDIOC_OMAP3ISP_STAT_REQ: Read statistics (AEWB/AF/histogram) data 43*4882a593Smuzhiyun * VIDIOC_OMAP3ISP_STAT_EN: Enable/disable a statistics module 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define VIDIOC_OMAP3ISP_CCDC_CFG \ 47*4882a593Smuzhiyun _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct omap3isp_ccdc_update_config) 48*4882a593Smuzhiyun #define VIDIOC_OMAP3ISP_PRV_CFG \ 49*4882a593Smuzhiyun _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct omap3isp_prev_update_config) 50*4882a593Smuzhiyun #define VIDIOC_OMAP3ISP_AEWB_CFG \ 51*4882a593Smuzhiyun _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct omap3isp_h3a_aewb_config) 52*4882a593Smuzhiyun #define VIDIOC_OMAP3ISP_HIST_CFG \ 53*4882a593Smuzhiyun _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct omap3isp_hist_config) 54*4882a593Smuzhiyun #define VIDIOC_OMAP3ISP_AF_CFG \ 55*4882a593Smuzhiyun _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct omap3isp_h3a_af_config) 56*4882a593Smuzhiyun #define VIDIOC_OMAP3ISP_STAT_REQ \ 57*4882a593Smuzhiyun _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct omap3isp_stat_data) 58*4882a593Smuzhiyun #define VIDIOC_OMAP3ISP_STAT_REQ_TIME32 \ 59*4882a593Smuzhiyun _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct omap3isp_stat_data_time32) 60*4882a593Smuzhiyun #define VIDIOC_OMAP3ISP_STAT_EN \ 61*4882a593Smuzhiyun _IOWR('V', BASE_VIDIOC_PRIVATE + 7, unsigned long) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * Events 65*4882a593Smuzhiyun * 66*4882a593Smuzhiyun * V4L2_EVENT_OMAP3ISP_AEWB: AEWB statistics data ready 67*4882a593Smuzhiyun * V4L2_EVENT_OMAP3ISP_AF: AF statistics data ready 68*4882a593Smuzhiyun * V4L2_EVENT_OMAP3ISP_HIST: Histogram statistics data ready 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define V4L2_EVENT_OMAP3ISP_CLASS (V4L2_EVENT_PRIVATE_START | 0x100) 72*4882a593Smuzhiyun #define V4L2_EVENT_OMAP3ISP_AEWB (V4L2_EVENT_OMAP3ISP_CLASS | 0x1) 73*4882a593Smuzhiyun #define V4L2_EVENT_OMAP3ISP_AF (V4L2_EVENT_OMAP3ISP_CLASS | 0x2) 74*4882a593Smuzhiyun #define V4L2_EVENT_OMAP3ISP_HIST (V4L2_EVENT_OMAP3ISP_CLASS | 0x3) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun struct omap3isp_stat_event_status { 77*4882a593Smuzhiyun __u32 frame_number; 78*4882a593Smuzhiyun __u16 config_counter; 79*4882a593Smuzhiyun __u8 buf_err; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* AE/AWB related structures and flags*/ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* H3A Range Constants */ 85*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MAX_SATURATION_LIM 1023 86*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MIN_WIN_H 2 87*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MAX_WIN_H 256 88*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MIN_WIN_W 6 89*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MAX_WIN_W 256 90*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MIN_WINVC 1 91*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MIN_WINHC 1 92*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MAX_WINVC 128 93*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MAX_WINHC 36 94*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MAX_WINSTART 4095 95*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MIN_SUB_INC 2 96*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MAX_SUB_INC 32 97*4882a593Smuzhiyun #define OMAP3ISP_AEWB_MAX_BUF_SIZE 83600 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #define OMAP3ISP_AF_IIRSH_MIN 0 100*4882a593Smuzhiyun #define OMAP3ISP_AF_IIRSH_MAX 4095 101*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MIN 1 102*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MAX 36 103*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MIN 1 104*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MAX 128 105*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_INCREMENT_MIN 2 106*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_INCREMENT_MAX 32 107*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_HEIGHT_MIN 2 108*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_HEIGHT_MAX 256 109*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_WIDTH_MIN 16 110*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_WIDTH_MAX 256 111*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_HZSTART_MIN 1 112*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_HZSTART_MAX 4095 113*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_VTSTART_MIN 0 114*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_VTSTART_MAX 4095 115*4882a593Smuzhiyun #define OMAP3ISP_AF_THRESHOLD_MAX 255 116*4882a593Smuzhiyun #define OMAP3ISP_AF_COEF_MAX 4095 117*4882a593Smuzhiyun #define OMAP3ISP_AF_PAXEL_SIZE 48 118*4882a593Smuzhiyun #define OMAP3ISP_AF_MAX_BUF_SIZE 221184 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /** 121*4882a593Smuzhiyun * struct omap3isp_h3a_aewb_config - AE AWB configuration reset values 122*4882a593Smuzhiyun * saturation_limit: Saturation limit. 123*4882a593Smuzhiyun * @win_height: Window Height. Range 2 - 256, even values only. 124*4882a593Smuzhiyun * @win_width: Window Width. Range 6 - 256, even values only. 125*4882a593Smuzhiyun * @ver_win_count: Vertical Window Count. Range 1 - 128. 126*4882a593Smuzhiyun * @hor_win_count: Horizontal Window Count. Range 1 - 36. 127*4882a593Smuzhiyun * @ver_win_start: Vertical Window Start. Range 0 - 4095. 128*4882a593Smuzhiyun * @hor_win_start: Horizontal Window Start. Range 0 - 4095. 129*4882a593Smuzhiyun * @blk_ver_win_start: Black Vertical Windows Start. Range 0 - 4095. 130*4882a593Smuzhiyun * @blk_win_height: Black Window Height. Range 2 - 256, even values only. 131*4882a593Smuzhiyun * @subsample_ver_inc: Subsample Vertical points increment Range 2 - 32, even 132*4882a593Smuzhiyun * values only. 133*4882a593Smuzhiyun * @subsample_hor_inc: Subsample Horizontal points increment Range 2 - 32, even 134*4882a593Smuzhiyun * values only. 135*4882a593Smuzhiyun * @alaw_enable: AEW ALAW EN flag. 136*4882a593Smuzhiyun */ 137*4882a593Smuzhiyun struct omap3isp_h3a_aewb_config { 138*4882a593Smuzhiyun /* 139*4882a593Smuzhiyun * Common fields. 140*4882a593Smuzhiyun * They should be the first ones and must be in the same order as in 141*4882a593Smuzhiyun * ispstat_generic_config struct. 142*4882a593Smuzhiyun */ 143*4882a593Smuzhiyun __u32 buf_size; 144*4882a593Smuzhiyun __u16 config_counter; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* Private fields */ 147*4882a593Smuzhiyun __u16 saturation_limit; 148*4882a593Smuzhiyun __u16 win_height; 149*4882a593Smuzhiyun __u16 win_width; 150*4882a593Smuzhiyun __u16 ver_win_count; 151*4882a593Smuzhiyun __u16 hor_win_count; 152*4882a593Smuzhiyun __u16 ver_win_start; 153*4882a593Smuzhiyun __u16 hor_win_start; 154*4882a593Smuzhiyun __u16 blk_ver_win_start; 155*4882a593Smuzhiyun __u16 blk_win_height; 156*4882a593Smuzhiyun __u16 subsample_ver_inc; 157*4882a593Smuzhiyun __u16 subsample_hor_inc; 158*4882a593Smuzhiyun __u8 alaw_enable; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /** 162*4882a593Smuzhiyun * struct omap3isp_stat_data - Statistic data sent to or received from user 163*4882a593Smuzhiyun * @ts: Timestamp of returned framestats. 164*4882a593Smuzhiyun * @buf: Pointer to pass to user. 165*4882a593Smuzhiyun * @frame_number: Frame number of requested stats. 166*4882a593Smuzhiyun * @cur_frame: Current frame number being processed. 167*4882a593Smuzhiyun * @config_counter: Number of the configuration associated with the data. 168*4882a593Smuzhiyun */ 169*4882a593Smuzhiyun struct omap3isp_stat_data { 170*4882a593Smuzhiyun #ifdef __KERNEL__ 171*4882a593Smuzhiyun struct { 172*4882a593Smuzhiyun __s64 tv_sec; 173*4882a593Smuzhiyun __s64 tv_usec; 174*4882a593Smuzhiyun } ts; 175*4882a593Smuzhiyun #else 176*4882a593Smuzhiyun struct timeval ts; 177*4882a593Smuzhiyun #endif 178*4882a593Smuzhiyun void __user *buf; 179*4882a593Smuzhiyun __u32 buf_size; 180*4882a593Smuzhiyun __u16 frame_number; 181*4882a593Smuzhiyun __u16 cur_frame; 182*4882a593Smuzhiyun __u16 config_counter; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #ifdef __KERNEL__ 186*4882a593Smuzhiyun struct omap3isp_stat_data_time32 { 187*4882a593Smuzhiyun struct { 188*4882a593Smuzhiyun __s32 tv_sec; 189*4882a593Smuzhiyun __s32 tv_usec; 190*4882a593Smuzhiyun } ts; 191*4882a593Smuzhiyun __u32 buf; 192*4882a593Smuzhiyun __u32 buf_size; 193*4882a593Smuzhiyun __u16 frame_number; 194*4882a593Smuzhiyun __u16 cur_frame; 195*4882a593Smuzhiyun __u16 config_counter; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun #endif 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* Histogram related structs */ 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun /* Flags for number of bins */ 202*4882a593Smuzhiyun #define OMAP3ISP_HIST_BINS_32 0 203*4882a593Smuzhiyun #define OMAP3ISP_HIST_BINS_64 1 204*4882a593Smuzhiyun #define OMAP3ISP_HIST_BINS_128 2 205*4882a593Smuzhiyun #define OMAP3ISP_HIST_BINS_256 3 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* Number of bins * 4 colors * 4-bytes word */ 208*4882a593Smuzhiyun #define OMAP3ISP_HIST_MEM_SIZE_BINS(n) ((1 << ((n)+5))*4*4) 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #define OMAP3ISP_HIST_MEM_SIZE 1024 211*4882a593Smuzhiyun #define OMAP3ISP_HIST_MIN_REGIONS 1 212*4882a593Smuzhiyun #define OMAP3ISP_HIST_MAX_REGIONS 4 213*4882a593Smuzhiyun #define OMAP3ISP_HIST_MAX_WB_GAIN 255 214*4882a593Smuzhiyun #define OMAP3ISP_HIST_MIN_WB_GAIN 0 215*4882a593Smuzhiyun #define OMAP3ISP_HIST_MAX_BIT_WIDTH 14 216*4882a593Smuzhiyun #define OMAP3ISP_HIST_MIN_BIT_WIDTH 8 217*4882a593Smuzhiyun #define OMAP3ISP_HIST_MAX_WG 4 218*4882a593Smuzhiyun #define OMAP3ISP_HIST_MAX_BUF_SIZE 4096 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /* Source */ 221*4882a593Smuzhiyun #define OMAP3ISP_HIST_SOURCE_CCDC 0 222*4882a593Smuzhiyun #define OMAP3ISP_HIST_SOURCE_MEM 1 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /* CFA pattern */ 225*4882a593Smuzhiyun #define OMAP3ISP_HIST_CFA_BAYER 0 226*4882a593Smuzhiyun #define OMAP3ISP_HIST_CFA_FOVEONX3 1 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun struct omap3isp_hist_region { 229*4882a593Smuzhiyun __u16 h_start; 230*4882a593Smuzhiyun __u16 h_end; 231*4882a593Smuzhiyun __u16 v_start; 232*4882a593Smuzhiyun __u16 v_end; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun struct omap3isp_hist_config { 236*4882a593Smuzhiyun /* 237*4882a593Smuzhiyun * Common fields. 238*4882a593Smuzhiyun * They should be the first ones and must be in the same order as in 239*4882a593Smuzhiyun * ispstat_generic_config struct. 240*4882a593Smuzhiyun */ 241*4882a593Smuzhiyun __u32 buf_size; 242*4882a593Smuzhiyun __u16 config_counter; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun __u8 num_acc_frames; /* Num of image frames to be processed and 245*4882a593Smuzhiyun accumulated for each histogram frame */ 246*4882a593Smuzhiyun __u16 hist_bins; /* number of bins: 32, 64, 128, or 256 */ 247*4882a593Smuzhiyun __u8 cfa; /* BAYER or FOVEON X3 */ 248*4882a593Smuzhiyun __u8 wg[OMAP3ISP_HIST_MAX_WG]; /* White Balance Gain */ 249*4882a593Smuzhiyun __u8 num_regions; /* number of regions to be configured */ 250*4882a593Smuzhiyun struct omap3isp_hist_region region[OMAP3ISP_HIST_MAX_REGIONS]; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun /* Auto Focus related structs */ 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun #define OMAP3ISP_AF_NUM_COEF 11 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun enum omap3isp_h3a_af_fvmode { 258*4882a593Smuzhiyun OMAP3ISP_AF_MODE_SUMMED = 0, 259*4882a593Smuzhiyun OMAP3ISP_AF_MODE_PEAK = 1 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun /* Red, Green, and blue pixel location in the AF windows */ 263*4882a593Smuzhiyun enum omap3isp_h3a_af_rgbpos { 264*4882a593Smuzhiyun OMAP3ISP_AF_GR_GB_BAYER = 0, /* GR and GB as Bayer pattern */ 265*4882a593Smuzhiyun OMAP3ISP_AF_RG_GB_BAYER = 1, /* RG and GB as Bayer pattern */ 266*4882a593Smuzhiyun OMAP3ISP_AF_GR_BG_BAYER = 2, /* GR and BG as Bayer pattern */ 267*4882a593Smuzhiyun OMAP3ISP_AF_RG_BG_BAYER = 3, /* RG and BG as Bayer pattern */ 268*4882a593Smuzhiyun OMAP3ISP_AF_GG_RB_CUSTOM = 4, /* GG and RB as custom pattern */ 269*4882a593Smuzhiyun OMAP3ISP_AF_RB_GG_CUSTOM = 5 /* RB and GG as custom pattern */ 270*4882a593Smuzhiyun }; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun /* Contains the information regarding the Horizontal Median Filter */ 273*4882a593Smuzhiyun struct omap3isp_h3a_af_hmf { 274*4882a593Smuzhiyun __u8 enable; /* Status of Horizontal Median Filter */ 275*4882a593Smuzhiyun __u8 threshold; /* Threshold Value for Horizontal Median Filter */ 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun /* Contains the information regarding the IIR Filters */ 279*4882a593Smuzhiyun struct omap3isp_h3a_af_iir { 280*4882a593Smuzhiyun __u16 h_start; /* IIR horizontal start */ 281*4882a593Smuzhiyun __u16 coeff_set0[OMAP3ISP_AF_NUM_COEF]; /* Filter coefficient, set 0 */ 282*4882a593Smuzhiyun __u16 coeff_set1[OMAP3ISP_AF_NUM_COEF]; /* Filter coefficient, set 1 */ 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun /* Contains the information regarding the Paxels Structure in AF Engine */ 286*4882a593Smuzhiyun struct omap3isp_h3a_af_paxel { 287*4882a593Smuzhiyun __u16 h_start; /* Horizontal Start Position */ 288*4882a593Smuzhiyun __u16 v_start; /* Vertical Start Position */ 289*4882a593Smuzhiyun __u8 width; /* Width of the Paxel */ 290*4882a593Smuzhiyun __u8 height; /* Height of the Paxel */ 291*4882a593Smuzhiyun __u8 h_cnt; /* Horizontal Count */ 292*4882a593Smuzhiyun __u8 v_cnt; /* vertical Count */ 293*4882a593Smuzhiyun __u8 line_inc; /* Line Increment */ 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun /* Contains the parameters required for hardware set up of AF Engine */ 297*4882a593Smuzhiyun struct omap3isp_h3a_af_config { 298*4882a593Smuzhiyun /* 299*4882a593Smuzhiyun * Common fields. 300*4882a593Smuzhiyun * They should be the first ones and must be in the same order as in 301*4882a593Smuzhiyun * ispstat_generic_config struct. 302*4882a593Smuzhiyun */ 303*4882a593Smuzhiyun __u32 buf_size; 304*4882a593Smuzhiyun __u16 config_counter; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun struct omap3isp_h3a_af_hmf hmf; /* HMF configurations */ 307*4882a593Smuzhiyun struct omap3isp_h3a_af_iir iir; /* IIR filter configurations */ 308*4882a593Smuzhiyun struct omap3isp_h3a_af_paxel paxel; /* Paxel parameters */ 309*4882a593Smuzhiyun enum omap3isp_h3a_af_rgbpos rgb_pos; /* RGB Positions */ 310*4882a593Smuzhiyun enum omap3isp_h3a_af_fvmode fvmode; /* Accumulator mode */ 311*4882a593Smuzhiyun __u8 alaw_enable; /* AF ALAW status */ 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* ISP CCDC structs */ 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun /* Abstraction layer CCDC configurations */ 317*4882a593Smuzhiyun #define OMAP3ISP_CCDC_ALAW (1 << 0) 318*4882a593Smuzhiyun #define OMAP3ISP_CCDC_LPF (1 << 1) 319*4882a593Smuzhiyun #define OMAP3ISP_CCDC_BLCLAMP (1 << 2) 320*4882a593Smuzhiyun #define OMAP3ISP_CCDC_BCOMP (1 << 3) 321*4882a593Smuzhiyun #define OMAP3ISP_CCDC_FPC (1 << 4) 322*4882a593Smuzhiyun #define OMAP3ISP_CCDC_CULL (1 << 5) 323*4882a593Smuzhiyun #define OMAP3ISP_CCDC_CONFIG_LSC (1 << 7) 324*4882a593Smuzhiyun #define OMAP3ISP_CCDC_TBL_LSC (1 << 8) 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun #define OMAP3ISP_RGB_MAX 3 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun /* Enumeration constants for Alaw input width */ 329*4882a593Smuzhiyun enum omap3isp_alaw_ipwidth { 330*4882a593Smuzhiyun OMAP3ISP_ALAW_BIT12_3 = 0x3, 331*4882a593Smuzhiyun OMAP3ISP_ALAW_BIT11_2 = 0x4, 332*4882a593Smuzhiyun OMAP3ISP_ALAW_BIT10_1 = 0x5, 333*4882a593Smuzhiyun OMAP3ISP_ALAW_BIT9_0 = 0x6 334*4882a593Smuzhiyun }; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun /** 337*4882a593Smuzhiyun * struct omap3isp_ccdc_lsc_config - LSC configuration 338*4882a593Smuzhiyun * @offset: Table Offset of the gain table. 339*4882a593Smuzhiyun * @gain_mode_n: Vertical dimension of a paxel in LSC configuration. 340*4882a593Smuzhiyun * @gain_mode_m: Horizontal dimension of a paxel in LSC configuration. 341*4882a593Smuzhiyun * @gain_format: Gain table format. 342*4882a593Smuzhiyun * @fmtsph: Start pixel horizontal from start of the HS sync pulse. 343*4882a593Smuzhiyun * @fmtlnh: Number of pixels in horizontal direction to use for the data 344*4882a593Smuzhiyun * reformatter. 345*4882a593Smuzhiyun * @fmtslv: Start line from start of VS sync pulse for the data reformatter. 346*4882a593Smuzhiyun * @fmtlnv: Number of lines in vertical direction for the data reformatter. 347*4882a593Smuzhiyun * @initial_x: X position, in pixels, of the first active pixel in reference 348*4882a593Smuzhiyun * to the first active paxel. Must be an even number. 349*4882a593Smuzhiyun * @initial_y: Y position, in pixels, of the first active pixel in reference 350*4882a593Smuzhiyun * to the first active paxel. Must be an even number. 351*4882a593Smuzhiyun * @size: Size of LSC gain table. Filled when loaded from userspace. 352*4882a593Smuzhiyun */ 353*4882a593Smuzhiyun struct omap3isp_ccdc_lsc_config { 354*4882a593Smuzhiyun __u16 offset; 355*4882a593Smuzhiyun __u8 gain_mode_n; 356*4882a593Smuzhiyun __u8 gain_mode_m; 357*4882a593Smuzhiyun __u8 gain_format; 358*4882a593Smuzhiyun __u16 fmtsph; 359*4882a593Smuzhiyun __u16 fmtlnh; 360*4882a593Smuzhiyun __u16 fmtslv; 361*4882a593Smuzhiyun __u16 fmtlnv; 362*4882a593Smuzhiyun __u8 initial_x; 363*4882a593Smuzhiyun __u8 initial_y; 364*4882a593Smuzhiyun __u32 size; 365*4882a593Smuzhiyun }; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun /** 368*4882a593Smuzhiyun * struct omap3isp_ccdc_bclamp - Optical & Digital black clamp subtract 369*4882a593Smuzhiyun * @obgain: Optical black average gain. 370*4882a593Smuzhiyun * @obstpixel: Start Pixel w.r.t. HS pulse in Optical black sample. 371*4882a593Smuzhiyun * @oblines: Optical Black Sample lines. 372*4882a593Smuzhiyun * @oblen: Optical Black Sample Length. 373*4882a593Smuzhiyun * @dcsubval: Digital Black Clamp subtract value. 374*4882a593Smuzhiyun */ 375*4882a593Smuzhiyun struct omap3isp_ccdc_bclamp { 376*4882a593Smuzhiyun __u8 obgain; 377*4882a593Smuzhiyun __u8 obstpixel; 378*4882a593Smuzhiyun __u8 oblines; 379*4882a593Smuzhiyun __u8 oblen; 380*4882a593Smuzhiyun __u16 dcsubval; 381*4882a593Smuzhiyun }; 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun /** 384*4882a593Smuzhiyun * struct omap3isp_ccdc_fpc - Faulty Pixels Correction 385*4882a593Smuzhiyun * @fpnum: Number of faulty pixels to be corrected in the frame. 386*4882a593Smuzhiyun * @fpcaddr: Memory address of the FPC Table 387*4882a593Smuzhiyun */ 388*4882a593Smuzhiyun struct omap3isp_ccdc_fpc { 389*4882a593Smuzhiyun __u16 fpnum; 390*4882a593Smuzhiyun __u32 fpcaddr; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun /** 394*4882a593Smuzhiyun * struct omap3isp_ccdc_blcomp - Black Level Compensation parameters 395*4882a593Smuzhiyun * @b_mg: B/Mg pixels. 2's complement. -128 to +127. 396*4882a593Smuzhiyun * @gb_g: Gb/G pixels. 2's complement. -128 to +127. 397*4882a593Smuzhiyun * @gr_cy: Gr/Cy pixels. 2's complement. -128 to +127. 398*4882a593Smuzhiyun * @r_ye: R/Ye pixels. 2's complement. -128 to +127. 399*4882a593Smuzhiyun */ 400*4882a593Smuzhiyun struct omap3isp_ccdc_blcomp { 401*4882a593Smuzhiyun __u8 b_mg; 402*4882a593Smuzhiyun __u8 gb_g; 403*4882a593Smuzhiyun __u8 gr_cy; 404*4882a593Smuzhiyun __u8 r_ye; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun /** 408*4882a593Smuzhiyun * omap3isp_ccdc_culling - Culling parameters 409*4882a593Smuzhiyun * @v_pattern: Vertical culling pattern. 410*4882a593Smuzhiyun * @h_odd: Horizontal Culling pattern for odd lines. 411*4882a593Smuzhiyun * @h_even: Horizontal Culling pattern for even lines. 412*4882a593Smuzhiyun */ 413*4882a593Smuzhiyun struct omap3isp_ccdc_culling { 414*4882a593Smuzhiyun __u8 v_pattern; 415*4882a593Smuzhiyun __u16 h_odd; 416*4882a593Smuzhiyun __u16 h_even; 417*4882a593Smuzhiyun }; 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun /** 420*4882a593Smuzhiyun * omap3isp_ccdc_update_config - CCDC configuration 421*4882a593Smuzhiyun * @update: Specifies which CCDC registers should be updated. 422*4882a593Smuzhiyun * @flag: Specifies which CCDC functions should be enabled. 423*4882a593Smuzhiyun * @alawip: Enable/Disable A-Law compression. 424*4882a593Smuzhiyun * @bclamp: Black clamp control register. 425*4882a593Smuzhiyun * @blcomp: Black level compensation value for RGrGbB Pixels. 2's complement. 426*4882a593Smuzhiyun * @fpc: Number of faulty pixels corrected in the frame, address of FPC table. 427*4882a593Smuzhiyun * @cull: Cull control register. 428*4882a593Smuzhiyun * @lsc: Pointer to LSC gain table. 429*4882a593Smuzhiyun */ 430*4882a593Smuzhiyun struct omap3isp_ccdc_update_config { 431*4882a593Smuzhiyun __u16 update; 432*4882a593Smuzhiyun __u16 flag; 433*4882a593Smuzhiyun enum omap3isp_alaw_ipwidth alawip; 434*4882a593Smuzhiyun struct omap3isp_ccdc_bclamp __user *bclamp; 435*4882a593Smuzhiyun struct omap3isp_ccdc_blcomp __user *blcomp; 436*4882a593Smuzhiyun struct omap3isp_ccdc_fpc __user *fpc; 437*4882a593Smuzhiyun struct omap3isp_ccdc_lsc_config __user *lsc_cfg; 438*4882a593Smuzhiyun struct omap3isp_ccdc_culling __user *cull; 439*4882a593Smuzhiyun __u8 __user *lsc; 440*4882a593Smuzhiyun }; 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun /* Preview configurations */ 443*4882a593Smuzhiyun #define OMAP3ISP_PREV_LUMAENH (1 << 0) 444*4882a593Smuzhiyun #define OMAP3ISP_PREV_INVALAW (1 << 1) 445*4882a593Smuzhiyun #define OMAP3ISP_PREV_HRZ_MED (1 << 2) 446*4882a593Smuzhiyun #define OMAP3ISP_PREV_CFA (1 << 3) 447*4882a593Smuzhiyun #define OMAP3ISP_PREV_CHROMA_SUPP (1 << 4) 448*4882a593Smuzhiyun #define OMAP3ISP_PREV_WB (1 << 5) 449*4882a593Smuzhiyun #define OMAP3ISP_PREV_BLKADJ (1 << 6) 450*4882a593Smuzhiyun #define OMAP3ISP_PREV_RGB2RGB (1 << 7) 451*4882a593Smuzhiyun #define OMAP3ISP_PREV_COLOR_CONV (1 << 8) 452*4882a593Smuzhiyun #define OMAP3ISP_PREV_YC_LIMIT (1 << 9) 453*4882a593Smuzhiyun #define OMAP3ISP_PREV_DEFECT_COR (1 << 10) 454*4882a593Smuzhiyun /* Bit 11 was OMAP3ISP_PREV_GAMMABYPASS, now merged with OMAP3ISP_PREV_GAMMA */ 455*4882a593Smuzhiyun #define OMAP3ISP_PREV_DRK_FRM_CAPTURE (1 << 12) 456*4882a593Smuzhiyun #define OMAP3ISP_PREV_DRK_FRM_SUBTRACT (1 << 13) 457*4882a593Smuzhiyun #define OMAP3ISP_PREV_LENS_SHADING (1 << 14) 458*4882a593Smuzhiyun #define OMAP3ISP_PREV_NF (1 << 15) 459*4882a593Smuzhiyun #define OMAP3ISP_PREV_GAMMA (1 << 16) 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun #define OMAP3ISP_PREV_NF_TBL_SIZE 64 462*4882a593Smuzhiyun #define OMAP3ISP_PREV_CFA_TBL_SIZE 576 463*4882a593Smuzhiyun #define OMAP3ISP_PREV_CFA_BLK_SIZE (OMAP3ISP_PREV_CFA_TBL_SIZE / 4) 464*4882a593Smuzhiyun #define OMAP3ISP_PREV_GAMMA_TBL_SIZE 1024 465*4882a593Smuzhiyun #define OMAP3ISP_PREV_YENH_TBL_SIZE 128 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun #define OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS 4 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun /** 470*4882a593Smuzhiyun * struct omap3isp_prev_hmed - Horizontal Median Filter 471*4882a593Smuzhiyun * @odddist: Distance between consecutive pixels of same color in the odd line. 472*4882a593Smuzhiyun * @evendist: Distance between consecutive pixels of same color in the even 473*4882a593Smuzhiyun * line. 474*4882a593Smuzhiyun * @thres: Horizontal median filter threshold. 475*4882a593Smuzhiyun */ 476*4882a593Smuzhiyun struct omap3isp_prev_hmed { 477*4882a593Smuzhiyun __u8 odddist; 478*4882a593Smuzhiyun __u8 evendist; 479*4882a593Smuzhiyun __u8 thres; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun /* 483*4882a593Smuzhiyun * Enumeration for CFA Formats supported by preview 484*4882a593Smuzhiyun */ 485*4882a593Smuzhiyun enum omap3isp_cfa_fmt { 486*4882a593Smuzhiyun OMAP3ISP_CFAFMT_BAYER, 487*4882a593Smuzhiyun OMAP3ISP_CFAFMT_SONYVGA, 488*4882a593Smuzhiyun OMAP3ISP_CFAFMT_RGBFOVEON, 489*4882a593Smuzhiyun OMAP3ISP_CFAFMT_DNSPL, 490*4882a593Smuzhiyun OMAP3ISP_CFAFMT_HONEYCOMB, 491*4882a593Smuzhiyun OMAP3ISP_CFAFMT_RRGGBBFOVEON 492*4882a593Smuzhiyun }; 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun /** 495*4882a593Smuzhiyun * struct omap3isp_prev_cfa - CFA Interpolation 496*4882a593Smuzhiyun * @format: CFA Format Enum value supported by preview. 497*4882a593Smuzhiyun * @gradthrs_vert: CFA Gradient Threshold - Vertical. 498*4882a593Smuzhiyun * @gradthrs_horz: CFA Gradient Threshold - Horizontal. 499*4882a593Smuzhiyun * @table: Pointer to the CFA table. 500*4882a593Smuzhiyun */ 501*4882a593Smuzhiyun struct omap3isp_prev_cfa { 502*4882a593Smuzhiyun enum omap3isp_cfa_fmt format; 503*4882a593Smuzhiyun __u8 gradthrs_vert; 504*4882a593Smuzhiyun __u8 gradthrs_horz; 505*4882a593Smuzhiyun __u32 table[4][OMAP3ISP_PREV_CFA_BLK_SIZE]; 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun /** 509*4882a593Smuzhiyun * struct omap3isp_prev_csup - Chrominance Suppression 510*4882a593Smuzhiyun * @gain: Gain. 511*4882a593Smuzhiyun * @thres: Threshold. 512*4882a593Smuzhiyun * @hypf_en: Flag to enable/disable the High Pass Filter. 513*4882a593Smuzhiyun */ 514*4882a593Smuzhiyun struct omap3isp_prev_csup { 515*4882a593Smuzhiyun __u8 gain; 516*4882a593Smuzhiyun __u8 thres; 517*4882a593Smuzhiyun __u8 hypf_en; 518*4882a593Smuzhiyun }; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun /** 521*4882a593Smuzhiyun * struct omap3isp_prev_wbal - White Balance 522*4882a593Smuzhiyun * @dgain: Digital gain (U10Q8). 523*4882a593Smuzhiyun * @coef3: White balance gain - COEF 3 (U8Q5). 524*4882a593Smuzhiyun * @coef2: White balance gain - COEF 2 (U8Q5). 525*4882a593Smuzhiyun * @coef1: White balance gain - COEF 1 (U8Q5). 526*4882a593Smuzhiyun * @coef0: White balance gain - COEF 0 (U8Q5). 527*4882a593Smuzhiyun */ 528*4882a593Smuzhiyun struct omap3isp_prev_wbal { 529*4882a593Smuzhiyun __u16 dgain; 530*4882a593Smuzhiyun __u8 coef3; 531*4882a593Smuzhiyun __u8 coef2; 532*4882a593Smuzhiyun __u8 coef1; 533*4882a593Smuzhiyun __u8 coef0; 534*4882a593Smuzhiyun }; 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun /** 537*4882a593Smuzhiyun * struct omap3isp_prev_blkadj - Black Level Adjustment 538*4882a593Smuzhiyun * @red: Black level offset adjustment for Red in 2's complement format 539*4882a593Smuzhiyun * @green: Black level offset adjustment for Green in 2's complement format 540*4882a593Smuzhiyun * @blue: Black level offset adjustment for Blue in 2's complement format 541*4882a593Smuzhiyun */ 542*4882a593Smuzhiyun struct omap3isp_prev_blkadj { 543*4882a593Smuzhiyun /*Black level offset adjustment for Red in 2's complement format */ 544*4882a593Smuzhiyun __u8 red; 545*4882a593Smuzhiyun /*Black level offset adjustment for Green in 2's complement format */ 546*4882a593Smuzhiyun __u8 green; 547*4882a593Smuzhiyun /* Black level offset adjustment for Blue in 2's complement format */ 548*4882a593Smuzhiyun __u8 blue; 549*4882a593Smuzhiyun }; 550*4882a593Smuzhiyun 551*4882a593Smuzhiyun /** 552*4882a593Smuzhiyun * struct omap3isp_prev_rgbtorgb - RGB to RGB Blending 553*4882a593Smuzhiyun * @matrix: Blending values(S12Q8 format) 554*4882a593Smuzhiyun * [RR] [GR] [BR] 555*4882a593Smuzhiyun * [RG] [GG] [BG] 556*4882a593Smuzhiyun * [RB] [GB] [BB] 557*4882a593Smuzhiyun * @offset: Blending offset value for R,G,B in 2's complement integer format. 558*4882a593Smuzhiyun */ 559*4882a593Smuzhiyun struct omap3isp_prev_rgbtorgb { 560*4882a593Smuzhiyun __u16 matrix[OMAP3ISP_RGB_MAX][OMAP3ISP_RGB_MAX]; 561*4882a593Smuzhiyun __u16 offset[OMAP3ISP_RGB_MAX]; 562*4882a593Smuzhiyun }; 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun /** 565*4882a593Smuzhiyun * struct omap3isp_prev_csc - Color Space Conversion from RGB-YCbYCr 566*4882a593Smuzhiyun * @matrix: Color space conversion coefficients(S10Q8) 567*4882a593Smuzhiyun * [CSCRY] [CSCGY] [CSCBY] 568*4882a593Smuzhiyun * [CSCRCB] [CSCGCB] [CSCBCB] 569*4882a593Smuzhiyun * [CSCRCR] [CSCGCR] [CSCBCR] 570*4882a593Smuzhiyun * @offset: CSC offset values for Y offset, CB offset and CR offset respectively 571*4882a593Smuzhiyun */ 572*4882a593Smuzhiyun struct omap3isp_prev_csc { 573*4882a593Smuzhiyun __u16 matrix[OMAP3ISP_RGB_MAX][OMAP3ISP_RGB_MAX]; 574*4882a593Smuzhiyun __s16 offset[OMAP3ISP_RGB_MAX]; 575*4882a593Smuzhiyun }; 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun /** 578*4882a593Smuzhiyun * struct omap3isp_prev_yclimit - Y, C Value Limit 579*4882a593Smuzhiyun * @minC: Minimum C value 580*4882a593Smuzhiyun * @maxC: Maximum C value 581*4882a593Smuzhiyun * @minY: Minimum Y value 582*4882a593Smuzhiyun * @maxY: Maximum Y value 583*4882a593Smuzhiyun */ 584*4882a593Smuzhiyun struct omap3isp_prev_yclimit { 585*4882a593Smuzhiyun __u8 minC; 586*4882a593Smuzhiyun __u8 maxC; 587*4882a593Smuzhiyun __u8 minY; 588*4882a593Smuzhiyun __u8 maxY; 589*4882a593Smuzhiyun }; 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun /** 592*4882a593Smuzhiyun * struct omap3isp_prev_dcor - Defect correction 593*4882a593Smuzhiyun * @couplet_mode_en: Flag to enable or disable the couplet dc Correction in NF 594*4882a593Smuzhiyun * @detect_correct: Thresholds for correction bit 0:10 detect 16:25 correct 595*4882a593Smuzhiyun */ 596*4882a593Smuzhiyun struct omap3isp_prev_dcor { 597*4882a593Smuzhiyun __u8 couplet_mode_en; 598*4882a593Smuzhiyun __u32 detect_correct[OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS]; 599*4882a593Smuzhiyun }; 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun /** 602*4882a593Smuzhiyun * struct omap3isp_prev_nf - Noise Filter 603*4882a593Smuzhiyun * @spread: Spread value to be used in Noise Filter 604*4882a593Smuzhiyun * @table: Pointer to the Noise Filter table 605*4882a593Smuzhiyun */ 606*4882a593Smuzhiyun struct omap3isp_prev_nf { 607*4882a593Smuzhiyun __u8 spread; 608*4882a593Smuzhiyun __u32 table[OMAP3ISP_PREV_NF_TBL_SIZE]; 609*4882a593Smuzhiyun }; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun /** 612*4882a593Smuzhiyun * struct omap3isp_prev_gtables - Gamma correction tables 613*4882a593Smuzhiyun * @red: Array for red gamma table. 614*4882a593Smuzhiyun * @green: Array for green gamma table. 615*4882a593Smuzhiyun * @blue: Array for blue gamma table. 616*4882a593Smuzhiyun */ 617*4882a593Smuzhiyun struct omap3isp_prev_gtables { 618*4882a593Smuzhiyun __u32 red[OMAP3ISP_PREV_GAMMA_TBL_SIZE]; 619*4882a593Smuzhiyun __u32 green[OMAP3ISP_PREV_GAMMA_TBL_SIZE]; 620*4882a593Smuzhiyun __u32 blue[OMAP3ISP_PREV_GAMMA_TBL_SIZE]; 621*4882a593Smuzhiyun }; 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun /** 624*4882a593Smuzhiyun * struct omap3isp_prev_luma - Luma enhancement 625*4882a593Smuzhiyun * @table: Array for luma enhancement table. 626*4882a593Smuzhiyun */ 627*4882a593Smuzhiyun struct omap3isp_prev_luma { 628*4882a593Smuzhiyun __u32 table[OMAP3ISP_PREV_YENH_TBL_SIZE]; 629*4882a593Smuzhiyun }; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun /** 632*4882a593Smuzhiyun * struct omap3isp_prev_update_config - Preview engine configuration (user) 633*4882a593Smuzhiyun * @update: Specifies which ISP Preview registers should be updated. 634*4882a593Smuzhiyun * @flag: Specifies which ISP Preview functions should be enabled. 635*4882a593Smuzhiyun * @shading_shift: 3bit value of shift used in shading compensation. 636*4882a593Smuzhiyun * @luma: Pointer to luma enhancement structure. 637*4882a593Smuzhiyun * @hmed: Pointer to structure containing the odd and even distance. 638*4882a593Smuzhiyun * between the pixels in the image along with the filter threshold. 639*4882a593Smuzhiyun * @cfa: Pointer to structure containing the CFA interpolation table, CFA. 640*4882a593Smuzhiyun * format in the image, vertical and horizontal gradient threshold. 641*4882a593Smuzhiyun * @csup: Pointer to Structure for Chrominance Suppression coefficients. 642*4882a593Smuzhiyun * @wbal: Pointer to structure for White Balance. 643*4882a593Smuzhiyun * @blkadj: Pointer to structure for Black Adjustment. 644*4882a593Smuzhiyun * @rgb2rgb: Pointer to structure for RGB to RGB Blending. 645*4882a593Smuzhiyun * @csc: Pointer to structure for Color Space Conversion from RGB-YCbYCr. 646*4882a593Smuzhiyun * @yclimit: Pointer to structure for Y, C Value Limit. 647*4882a593Smuzhiyun * @dcor: Pointer to structure for defect correction. 648*4882a593Smuzhiyun * @nf: Pointer to structure for Noise Filter 649*4882a593Smuzhiyun * @gamma: Pointer to gamma structure. 650*4882a593Smuzhiyun */ 651*4882a593Smuzhiyun struct omap3isp_prev_update_config { 652*4882a593Smuzhiyun __u32 update; 653*4882a593Smuzhiyun __u32 flag; 654*4882a593Smuzhiyun __u32 shading_shift; 655*4882a593Smuzhiyun struct omap3isp_prev_luma __user *luma; 656*4882a593Smuzhiyun struct omap3isp_prev_hmed __user *hmed; 657*4882a593Smuzhiyun struct omap3isp_prev_cfa __user *cfa; 658*4882a593Smuzhiyun struct omap3isp_prev_csup __user *csup; 659*4882a593Smuzhiyun struct omap3isp_prev_wbal __user *wbal; 660*4882a593Smuzhiyun struct omap3isp_prev_blkadj __user *blkadj; 661*4882a593Smuzhiyun struct omap3isp_prev_rgbtorgb __user *rgb2rgb; 662*4882a593Smuzhiyun struct omap3isp_prev_csc __user *csc; 663*4882a593Smuzhiyun struct omap3isp_prev_yclimit __user *yclimit; 664*4882a593Smuzhiyun struct omap3isp_prev_dcor __user *dcor; 665*4882a593Smuzhiyun struct omap3isp_prev_nf __user *nf; 666*4882a593Smuzhiyun struct omap3isp_prev_gtables __user *gamma; 667*4882a593Smuzhiyun }; 668*4882a593Smuzhiyun 669*4882a593Smuzhiyun #endif /* OMAP3_ISP_USER_H */ 670