xref: /OK3568_Linux_fs/kernel/include/uapi/linux/i2o-dev.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * I2O user space accessible structures/APIs
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * (c) Copyright 1999, 2000 Red Hat Software
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or
8*4882a593Smuzhiyun  * modify it under the terms of the GNU General Public License
9*4882a593Smuzhiyun  * as published by the Free Software Foundation; either version
10*4882a593Smuzhiyun  * 2 of the License, or (at your option) any later version.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  *************************************************************************
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * This header file defines the I2O APIs that are available to both
15*4882a593Smuzhiyun  * the kernel and user level applications.  Kernel specific structures
16*4882a593Smuzhiyun  * are defined in i2o_osm. OSMs should include _only_ i2o_osm.h which
17*4882a593Smuzhiyun  * automatically includes this file.
18*4882a593Smuzhiyun  *
19*4882a593Smuzhiyun  */
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #ifndef _I2O_DEV_H
22*4882a593Smuzhiyun #define _I2O_DEV_H
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun /* How many controllers are we allowing */
25*4882a593Smuzhiyun #define MAX_I2O_CONTROLLERS	32
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include <linux/ioctl.h>
28*4882a593Smuzhiyun #include <linux/types.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun  * I2O Control IOCTLs and structures
32*4882a593Smuzhiyun  */
33*4882a593Smuzhiyun #define I2O_MAGIC_NUMBER	'i'
34*4882a593Smuzhiyun #define I2OGETIOPS		_IOR(I2O_MAGIC_NUMBER,0,__u8[MAX_I2O_CONTROLLERS])
35*4882a593Smuzhiyun #define I2OHRTGET		_IOWR(I2O_MAGIC_NUMBER,1,struct i2o_cmd_hrtlct)
36*4882a593Smuzhiyun #define I2OLCTGET		_IOWR(I2O_MAGIC_NUMBER,2,struct i2o_cmd_hrtlct)
37*4882a593Smuzhiyun #define I2OPARMSET		_IOWR(I2O_MAGIC_NUMBER,3,struct i2o_cmd_psetget)
38*4882a593Smuzhiyun #define I2OPARMGET		_IOWR(I2O_MAGIC_NUMBER,4,struct i2o_cmd_psetget)
39*4882a593Smuzhiyun #define I2OSWDL 		_IOWR(I2O_MAGIC_NUMBER,5,struct i2o_sw_xfer)
40*4882a593Smuzhiyun #define I2OSWUL 		_IOWR(I2O_MAGIC_NUMBER,6,struct i2o_sw_xfer)
41*4882a593Smuzhiyun #define I2OSWDEL		_IOWR(I2O_MAGIC_NUMBER,7,struct i2o_sw_xfer)
42*4882a593Smuzhiyun #define I2OVALIDATE		_IOR(I2O_MAGIC_NUMBER,8,__u32)
43*4882a593Smuzhiyun #define I2OHTML 		_IOWR(I2O_MAGIC_NUMBER,9,struct i2o_html)
44*4882a593Smuzhiyun #define I2OEVTREG		_IOW(I2O_MAGIC_NUMBER,10,struct i2o_evt_id)
45*4882a593Smuzhiyun #define I2OEVTGET		_IOR(I2O_MAGIC_NUMBER,11,struct i2o_evt_info)
46*4882a593Smuzhiyun #define I2OPASSTHRU		_IOR(I2O_MAGIC_NUMBER,12,struct i2o_cmd_passthru)
47*4882a593Smuzhiyun #define I2OPASSTHRU32		_IOR(I2O_MAGIC_NUMBER,12,struct i2o_cmd_passthru32)
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun struct i2o_cmd_passthru32 {
50*4882a593Smuzhiyun 	unsigned int iop;	/* IOP unit number */
51*4882a593Smuzhiyun 	__u32 msg;		/* message */
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun struct i2o_cmd_passthru {
55*4882a593Smuzhiyun 	unsigned int iop;	/* IOP unit number */
56*4882a593Smuzhiyun 	void __user *msg;	/* message */
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun struct i2o_cmd_hrtlct {
60*4882a593Smuzhiyun 	unsigned int iop;	/* IOP unit number */
61*4882a593Smuzhiyun 	void __user *resbuf;	/* Buffer for result */
62*4882a593Smuzhiyun 	unsigned int __user *reslen;	/* Buffer length in bytes */
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun struct i2o_cmd_psetget {
66*4882a593Smuzhiyun 	unsigned int iop;	/* IOP unit number */
67*4882a593Smuzhiyun 	unsigned int tid;	/* Target device TID */
68*4882a593Smuzhiyun 	void __user *opbuf;	/* Operation List buffer */
69*4882a593Smuzhiyun 	unsigned int oplen;	/* Operation List buffer length in bytes */
70*4882a593Smuzhiyun 	void __user *resbuf;	/* Result List buffer */
71*4882a593Smuzhiyun 	unsigned int __user *reslen;	/* Result List buffer length in bytes */
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun struct i2o_sw_xfer {
75*4882a593Smuzhiyun 	unsigned int iop;	/* IOP unit number */
76*4882a593Smuzhiyun 	unsigned char flags;	/* Flags field */
77*4882a593Smuzhiyun 	unsigned char sw_type;	/* Software type */
78*4882a593Smuzhiyun 	unsigned int sw_id;	/* Software ID */
79*4882a593Smuzhiyun 	void __user *buf;	/* Pointer to software buffer */
80*4882a593Smuzhiyun 	unsigned int __user *swlen;	/* Length of software data */
81*4882a593Smuzhiyun 	unsigned int __user *maxfrag;	/* Maximum fragment count */
82*4882a593Smuzhiyun 	unsigned int __user *curfrag;	/* Current fragment count */
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun struct i2o_html {
86*4882a593Smuzhiyun 	unsigned int iop;	/* IOP unit number */
87*4882a593Smuzhiyun 	unsigned int tid;	/* Target device ID */
88*4882a593Smuzhiyun 	unsigned int page;	/* HTML page */
89*4882a593Smuzhiyun 	void __user *resbuf;	/* Buffer for reply HTML page */
90*4882a593Smuzhiyun 	unsigned int __user *reslen;	/* Length in bytes of reply buffer */
91*4882a593Smuzhiyun 	void __user *qbuf;	/* Pointer to HTTP query string */
92*4882a593Smuzhiyun 	unsigned int qlen;	/* Length in bytes of query string buffer */
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define I2O_EVT_Q_LEN 32
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun struct i2o_evt_id {
98*4882a593Smuzhiyun 	unsigned int iop;
99*4882a593Smuzhiyun 	unsigned int tid;
100*4882a593Smuzhiyun 	unsigned int evt_mask;
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* Event data size = frame size - message header + evt indicator */
104*4882a593Smuzhiyun #define I2O_EVT_DATA_SIZE 88
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun struct i2o_evt_info {
107*4882a593Smuzhiyun 	struct i2o_evt_id id;
108*4882a593Smuzhiyun 	unsigned char evt_data[I2O_EVT_DATA_SIZE];
109*4882a593Smuzhiyun 	unsigned int data_size;
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun struct i2o_evt_get {
113*4882a593Smuzhiyun 	struct i2o_evt_info info;
114*4882a593Smuzhiyun 	int pending;
115*4882a593Smuzhiyun 	int lost;
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun typedef struct i2o_sg_io_hdr {
119*4882a593Smuzhiyun 	unsigned int flags;	/* see I2O_DPT_SG_IO_FLAGS */
120*4882a593Smuzhiyun } i2o_sg_io_hdr_t;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /**************************************************************************
123*4882a593Smuzhiyun  * HRT related constants and structures
124*4882a593Smuzhiyun  **************************************************************************/
125*4882a593Smuzhiyun #define I2O_BUS_LOCAL	0
126*4882a593Smuzhiyun #define I2O_BUS_ISA	1
127*4882a593Smuzhiyun #define I2O_BUS_EISA	2
128*4882a593Smuzhiyun /* was  I2O_BUS_MCA	3 */
129*4882a593Smuzhiyun #define I2O_BUS_PCI	4
130*4882a593Smuzhiyun #define I2O_BUS_PCMCIA	5
131*4882a593Smuzhiyun #define I2O_BUS_NUBUS	6
132*4882a593Smuzhiyun #define I2O_BUS_CARDBUS 7
133*4882a593Smuzhiyun #define I2O_BUS_UNKNOWN 0x80
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun typedef struct _i2o_pci_bus {
136*4882a593Smuzhiyun 	__u8 PciFunctionNumber;
137*4882a593Smuzhiyun 	__u8 PciDeviceNumber;
138*4882a593Smuzhiyun 	__u8 PciBusNumber;
139*4882a593Smuzhiyun 	__u8 reserved;
140*4882a593Smuzhiyun 	__u16 PciVendorID;
141*4882a593Smuzhiyun 	__u16 PciDeviceID;
142*4882a593Smuzhiyun } i2o_pci_bus;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun typedef struct _i2o_local_bus {
145*4882a593Smuzhiyun 	__u16 LbBaseIOPort;
146*4882a593Smuzhiyun 	__u16 reserved;
147*4882a593Smuzhiyun 	__u32 LbBaseMemoryAddress;
148*4882a593Smuzhiyun } i2o_local_bus;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun typedef struct _i2o_isa_bus {
151*4882a593Smuzhiyun 	__u16 IsaBaseIOPort;
152*4882a593Smuzhiyun 	__u8 CSN;
153*4882a593Smuzhiyun 	__u8 reserved;
154*4882a593Smuzhiyun 	__u32 IsaBaseMemoryAddress;
155*4882a593Smuzhiyun } i2o_isa_bus;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun typedef struct _i2o_eisa_bus_info {
158*4882a593Smuzhiyun 	__u16 EisaBaseIOPort;
159*4882a593Smuzhiyun 	__u8 reserved;
160*4882a593Smuzhiyun 	__u8 EisaSlotNumber;
161*4882a593Smuzhiyun 	__u32 EisaBaseMemoryAddress;
162*4882a593Smuzhiyun } i2o_eisa_bus;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun typedef struct _i2o_mca_bus {
165*4882a593Smuzhiyun 	__u16 McaBaseIOPort;
166*4882a593Smuzhiyun 	__u8 reserved;
167*4882a593Smuzhiyun 	__u8 McaSlotNumber;
168*4882a593Smuzhiyun 	__u32 McaBaseMemoryAddress;
169*4882a593Smuzhiyun } i2o_mca_bus;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun typedef struct _i2o_other_bus {
172*4882a593Smuzhiyun 	__u16 BaseIOPort;
173*4882a593Smuzhiyun 	__u16 reserved;
174*4882a593Smuzhiyun 	__u32 BaseMemoryAddress;
175*4882a593Smuzhiyun } i2o_other_bus;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun typedef struct _i2o_hrt_entry {
178*4882a593Smuzhiyun 	__u32 adapter_id;
179*4882a593Smuzhiyun 	__u32 parent_tid:12;
180*4882a593Smuzhiyun 	__u32 state:4;
181*4882a593Smuzhiyun 	__u32 bus_num:8;
182*4882a593Smuzhiyun 	__u32 bus_type:8;
183*4882a593Smuzhiyun 	union {
184*4882a593Smuzhiyun 		i2o_pci_bus pci_bus;
185*4882a593Smuzhiyun 		i2o_local_bus local_bus;
186*4882a593Smuzhiyun 		i2o_isa_bus isa_bus;
187*4882a593Smuzhiyun 		i2o_eisa_bus eisa_bus;
188*4882a593Smuzhiyun 		i2o_mca_bus mca_bus;
189*4882a593Smuzhiyun 		i2o_other_bus other_bus;
190*4882a593Smuzhiyun 	} bus;
191*4882a593Smuzhiyun } i2o_hrt_entry;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun typedef struct _i2o_hrt {
194*4882a593Smuzhiyun 	__u16 num_entries;
195*4882a593Smuzhiyun 	__u8 entry_len;
196*4882a593Smuzhiyun 	__u8 hrt_version;
197*4882a593Smuzhiyun 	__u32 change_ind;
198*4882a593Smuzhiyun 	i2o_hrt_entry hrt_entry[1];
199*4882a593Smuzhiyun } i2o_hrt;
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun typedef struct _i2o_lct_entry {
202*4882a593Smuzhiyun 	__u32 entry_size:16;
203*4882a593Smuzhiyun 	__u32 tid:12;
204*4882a593Smuzhiyun 	__u32 reserved:4;
205*4882a593Smuzhiyun 	__u32 change_ind;
206*4882a593Smuzhiyun 	__u32 device_flags;
207*4882a593Smuzhiyun 	__u32 class_id:12;
208*4882a593Smuzhiyun 	__u32 version:4;
209*4882a593Smuzhiyun 	__u32 vendor_id:16;
210*4882a593Smuzhiyun 	__u32 sub_class;
211*4882a593Smuzhiyun 	__u32 user_tid:12;
212*4882a593Smuzhiyun 	__u32 parent_tid:12;
213*4882a593Smuzhiyun 	__u32 bios_info:8;
214*4882a593Smuzhiyun 	__u8 identity_tag[8];
215*4882a593Smuzhiyun 	__u32 event_capabilities;
216*4882a593Smuzhiyun } i2o_lct_entry;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun typedef struct _i2o_lct {
219*4882a593Smuzhiyun 	__u32 table_size:16;
220*4882a593Smuzhiyun 	__u32 boot_tid:12;
221*4882a593Smuzhiyun 	__u32 lct_ver:4;
222*4882a593Smuzhiyun 	__u32 iop_flags;
223*4882a593Smuzhiyun 	__u32 change_ind;
224*4882a593Smuzhiyun 	i2o_lct_entry lct_entry[1];
225*4882a593Smuzhiyun } i2o_lct;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun typedef struct _i2o_status_block {
228*4882a593Smuzhiyun 	__u16 org_id;
229*4882a593Smuzhiyun 	__u16 reserved;
230*4882a593Smuzhiyun 	__u16 iop_id:12;
231*4882a593Smuzhiyun 	__u16 reserved1:4;
232*4882a593Smuzhiyun 	__u16 host_unit_id;
233*4882a593Smuzhiyun 	__u16 segment_number:12;
234*4882a593Smuzhiyun 	__u16 i2o_version:4;
235*4882a593Smuzhiyun 	__u8 iop_state;
236*4882a593Smuzhiyun 	__u8 msg_type;
237*4882a593Smuzhiyun 	__u16 inbound_frame_size;
238*4882a593Smuzhiyun 	__u8 init_code;
239*4882a593Smuzhiyun 	__u8 reserved2;
240*4882a593Smuzhiyun 	__u32 max_inbound_frames;
241*4882a593Smuzhiyun 	__u32 cur_inbound_frames;
242*4882a593Smuzhiyun 	__u32 max_outbound_frames;
243*4882a593Smuzhiyun 	char product_id[24];
244*4882a593Smuzhiyun 	__u32 expected_lct_size;
245*4882a593Smuzhiyun 	__u32 iop_capabilities;
246*4882a593Smuzhiyun 	__u32 desired_mem_size;
247*4882a593Smuzhiyun 	__u32 current_mem_size;
248*4882a593Smuzhiyun 	__u32 current_mem_base;
249*4882a593Smuzhiyun 	__u32 desired_io_size;
250*4882a593Smuzhiyun 	__u32 current_io_size;
251*4882a593Smuzhiyun 	__u32 current_io_base;
252*4882a593Smuzhiyun 	__u32 reserved3:24;
253*4882a593Smuzhiyun 	__u32 cmd_status:8;
254*4882a593Smuzhiyun } i2o_status_block;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun /* Event indicator mask flags */
257*4882a593Smuzhiyun #define I2O_EVT_IND_STATE_CHANGE		0x80000000
258*4882a593Smuzhiyun #define I2O_EVT_IND_GENERAL_WARNING		0x40000000
259*4882a593Smuzhiyun #define I2O_EVT_IND_CONFIGURATION_FLAG		0x20000000
260*4882a593Smuzhiyun #define I2O_EVT_IND_LOCK_RELEASE		0x10000000
261*4882a593Smuzhiyun #define I2O_EVT_IND_CAPABILITY_CHANGE		0x08000000
262*4882a593Smuzhiyun #define I2O_EVT_IND_DEVICE_RESET		0x04000000
263*4882a593Smuzhiyun #define I2O_EVT_IND_EVT_MASK_MODIFIED		0x02000000
264*4882a593Smuzhiyun #define I2O_EVT_IND_FIELD_MODIFIED		0x01000000
265*4882a593Smuzhiyun #define I2O_EVT_IND_VENDOR_EVT			0x00800000
266*4882a593Smuzhiyun #define I2O_EVT_IND_DEVICE_STATE		0x00400000
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun /* Executive event indicitors */
269*4882a593Smuzhiyun #define I2O_EVT_IND_EXEC_RESOURCE_LIMITS	0x00000001
270*4882a593Smuzhiyun #define I2O_EVT_IND_EXEC_CONNECTION_FAIL	0x00000002
271*4882a593Smuzhiyun #define I2O_EVT_IND_EXEC_ADAPTER_FAULT		0x00000004
272*4882a593Smuzhiyun #define I2O_EVT_IND_EXEC_POWER_FAIL		0x00000008
273*4882a593Smuzhiyun #define I2O_EVT_IND_EXEC_RESET_PENDING		0x00000010
274*4882a593Smuzhiyun #define I2O_EVT_IND_EXEC_RESET_IMMINENT 	0x00000020
275*4882a593Smuzhiyun #define I2O_EVT_IND_EXEC_HW_FAIL		0x00000040
276*4882a593Smuzhiyun #define I2O_EVT_IND_EXEC_XCT_CHANGE		0x00000080
277*4882a593Smuzhiyun #define I2O_EVT_IND_EXEC_NEW_LCT_ENTRY		0x00000100
278*4882a593Smuzhiyun #define I2O_EVT_IND_EXEC_MODIFIED_LCT		0x00000200
279*4882a593Smuzhiyun #define I2O_EVT_IND_EXEC_DDM_AVAILABILITY	0x00000400
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun /* Random Block Storage Event Indicators */
282*4882a593Smuzhiyun #define I2O_EVT_IND_BSA_VOLUME_LOAD		0x00000001
283*4882a593Smuzhiyun #define I2O_EVT_IND_BSA_VOLUME_UNLOAD		0x00000002
284*4882a593Smuzhiyun #define I2O_EVT_IND_BSA_VOLUME_UNLOAD_REQ	0x00000004
285*4882a593Smuzhiyun #define I2O_EVT_IND_BSA_CAPACITY_CHANGE 	0x00000008
286*4882a593Smuzhiyun #define I2O_EVT_IND_BSA_SCSI_SMART		0x00000010
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun /* Event data for generic events */
289*4882a593Smuzhiyun #define I2O_EVT_STATE_CHANGE_NORMAL		0x00
290*4882a593Smuzhiyun #define I2O_EVT_STATE_CHANGE_SUSPENDED		0x01
291*4882a593Smuzhiyun #define I2O_EVT_STATE_CHANGE_RESTART		0x02
292*4882a593Smuzhiyun #define I2O_EVT_STATE_CHANGE_NA_RECOVER 	0x03
293*4882a593Smuzhiyun #define I2O_EVT_STATE_CHANGE_NA_NO_RECOVER	0x04
294*4882a593Smuzhiyun #define I2O_EVT_STATE_CHANGE_QUIESCE_REQUEST	0x05
295*4882a593Smuzhiyun #define I2O_EVT_STATE_CHANGE_FAILED		0x10
296*4882a593Smuzhiyun #define I2O_EVT_STATE_CHANGE_FAULTED		0x11
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun #define I2O_EVT_GEN_WARNING_NORMAL		0x00
299*4882a593Smuzhiyun #define I2O_EVT_GEN_WARNING_ERROR_THRESHOLD	0x01
300*4882a593Smuzhiyun #define I2O_EVT_GEN_WARNING_MEDIA_FAULT 	0x02
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun #define I2O_EVT_CAPABILITY_OTHER		0x01
303*4882a593Smuzhiyun #define I2O_EVT_CAPABILITY_CHANGED		0x02
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun #define I2O_EVT_SENSOR_STATE_CHANGED		0x01
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun /*
308*4882a593Smuzhiyun  *	I2O classes / subclasses
309*4882a593Smuzhiyun  */
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun /*  Class ID and Code Assignments
312*4882a593Smuzhiyun  *  (LCT.ClassID.Version field)
313*4882a593Smuzhiyun  */
314*4882a593Smuzhiyun #define I2O_CLASS_VERSION_10			0x00
315*4882a593Smuzhiyun #define I2O_CLASS_VERSION_11			0x01
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun /*  Class code names
318*4882a593Smuzhiyun  *  (from v1.5 Table 6-1 Class Code Assignments.)
319*4882a593Smuzhiyun  */
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun #define I2O_CLASS_EXECUTIVE			0x000
322*4882a593Smuzhiyun #define I2O_CLASS_DDM				0x001
323*4882a593Smuzhiyun #define I2O_CLASS_RANDOM_BLOCK_STORAGE		0x010
324*4882a593Smuzhiyun #define I2O_CLASS_SEQUENTIAL_STORAGE		0x011
325*4882a593Smuzhiyun #define I2O_CLASS_LAN				0x020
326*4882a593Smuzhiyun #define I2O_CLASS_WAN				0x030
327*4882a593Smuzhiyun #define I2O_CLASS_FIBRE_CHANNEL_PORT		0x040
328*4882a593Smuzhiyun #define I2O_CLASS_FIBRE_CHANNEL_PERIPHERAL	0x041
329*4882a593Smuzhiyun #define I2O_CLASS_SCSI_PERIPHERAL		0x051
330*4882a593Smuzhiyun #define I2O_CLASS_ATE_PORT			0x060
331*4882a593Smuzhiyun #define I2O_CLASS_ATE_PERIPHERAL		0x061
332*4882a593Smuzhiyun #define I2O_CLASS_FLOPPY_CONTROLLER		0x070
333*4882a593Smuzhiyun #define I2O_CLASS_FLOPPY_DEVICE 		0x071
334*4882a593Smuzhiyun #define I2O_CLASS_BUS_ADAPTER			0x080
335*4882a593Smuzhiyun #define I2O_CLASS_PEER_TRANSPORT_AGENT		0x090
336*4882a593Smuzhiyun #define I2O_CLASS_PEER_TRANSPORT		0x091
337*4882a593Smuzhiyun #define	I2O_CLASS_END				0xfff
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun /*
340*4882a593Smuzhiyun  *  Rest of 0x092 - 0x09f reserved for peer-to-peer classes
341*4882a593Smuzhiyun  */
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun #define I2O_CLASS_MATCH_ANYCLASS		0xffffffff
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun /*
346*4882a593Smuzhiyun  *  Subclasses
347*4882a593Smuzhiyun  */
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun #define I2O_SUBCLASS_i960			0x001
350*4882a593Smuzhiyun #define I2O_SUBCLASS_HDM			0x020
351*4882a593Smuzhiyun #define I2O_SUBCLASS_ISM			0x021
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun /* Operation functions */
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun #define I2O_PARAMS_FIELD_GET			0x0001
356*4882a593Smuzhiyun #define I2O_PARAMS_LIST_GET			0x0002
357*4882a593Smuzhiyun #define I2O_PARAMS_MORE_GET			0x0003
358*4882a593Smuzhiyun #define I2O_PARAMS_SIZE_GET			0x0004
359*4882a593Smuzhiyun #define I2O_PARAMS_TABLE_GET			0x0005
360*4882a593Smuzhiyun #define I2O_PARAMS_FIELD_SET			0x0006
361*4882a593Smuzhiyun #define I2O_PARAMS_LIST_SET			0x0007
362*4882a593Smuzhiyun #define I2O_PARAMS_ROW_ADD			0x0008
363*4882a593Smuzhiyun #define I2O_PARAMS_ROW_DELETE			0x0009
364*4882a593Smuzhiyun #define I2O_PARAMS_TABLE_CLEAR			0x000A
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun /*
367*4882a593Smuzhiyun  * I2O serial number conventions / formats
368*4882a593Smuzhiyun  * (circa v1.5)
369*4882a593Smuzhiyun  */
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun #define I2O_SNFORMAT_UNKNOWN			0
372*4882a593Smuzhiyun #define I2O_SNFORMAT_BINARY			1
373*4882a593Smuzhiyun #define I2O_SNFORMAT_ASCII			2
374*4882a593Smuzhiyun #define I2O_SNFORMAT_UNICODE			3
375*4882a593Smuzhiyun #define I2O_SNFORMAT_LAN48_MAC			4
376*4882a593Smuzhiyun #define I2O_SNFORMAT_WAN			5
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun /*
379*4882a593Smuzhiyun  * Plus new in v2.0 (Yellowstone pdf doc)
380*4882a593Smuzhiyun  */
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun #define I2O_SNFORMAT_LAN64_MAC			6
383*4882a593Smuzhiyun #define I2O_SNFORMAT_DDM			7
384*4882a593Smuzhiyun #define I2O_SNFORMAT_IEEE_REG64 		8
385*4882a593Smuzhiyun #define I2O_SNFORMAT_IEEE_REG128		9
386*4882a593Smuzhiyun #define I2O_SNFORMAT_UNKNOWN2			0xff
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun /*
389*4882a593Smuzhiyun  *	I2O Get Status State values
390*4882a593Smuzhiyun  */
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun #define ADAPTER_STATE_INITIALIZING		0x01
393*4882a593Smuzhiyun #define ADAPTER_STATE_RESET			0x02
394*4882a593Smuzhiyun #define ADAPTER_STATE_HOLD			0x04
395*4882a593Smuzhiyun #define ADAPTER_STATE_READY			0x05
396*4882a593Smuzhiyun #define ADAPTER_STATE_OPERATIONAL		0x08
397*4882a593Smuzhiyun #define ADAPTER_STATE_FAILED			0x10
398*4882a593Smuzhiyun #define ADAPTER_STATE_FAULTED			0x11
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun /*
401*4882a593Smuzhiyun  *	Software module types
402*4882a593Smuzhiyun  */
403*4882a593Smuzhiyun #define I2O_SOFTWARE_MODULE_IRTOS		0x11
404*4882a593Smuzhiyun #define I2O_SOFTWARE_MODULE_IOP_PRIVATE		0x22
405*4882a593Smuzhiyun #define I2O_SOFTWARE_MODULE_IOP_CONFIG		0x23
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun /*
408*4882a593Smuzhiyun  *	Vendors
409*4882a593Smuzhiyun  */
410*4882a593Smuzhiyun #define I2O_VENDOR_DPT				0x001b
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun /*
413*4882a593Smuzhiyun  * DPT / Adaptec specific values for i2o_sg_io_hdr flags.
414*4882a593Smuzhiyun  */
415*4882a593Smuzhiyun #define I2O_DPT_SG_FLAG_INTERPRET		0x00010000
416*4882a593Smuzhiyun #define I2O_DPT_SG_FLAG_PHYSICAL		0x00020000
417*4882a593Smuzhiyun 
418*4882a593Smuzhiyun #define I2O_DPT_FLASH_FRAG_SIZE			0x10000
419*4882a593Smuzhiyun #define I2O_DPT_FLASH_READ			0x0101
420*4882a593Smuzhiyun #define I2O_DPT_FLASH_WRITE			0x0102
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun #endif				/* _I2O_DEV_H */
423