xref: /OK3568_Linux_fs/kernel/include/uapi/drm/virtgpu_drm.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2013 Red Hat
3*4882a593Smuzhiyun  * All Rights Reserved.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
6*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
7*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
8*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
10*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * The above copyright notice and this permission notice (including the next
13*4882a593Smuzhiyun  * paragraph) shall be included in all copies or substantial portions of the
14*4882a593Smuzhiyun  * Software.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19*4882a593Smuzhiyun  * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22*4882a593Smuzhiyun  * OTHER DEALINGS IN THE SOFTWARE.
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun #ifndef VIRTGPU_DRM_H
25*4882a593Smuzhiyun #define VIRTGPU_DRM_H
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "drm.h"
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #if defined(__cplusplus)
30*4882a593Smuzhiyun extern "C" {
31*4882a593Smuzhiyun #endif
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* Please note that modifications to all structs defined here are
34*4882a593Smuzhiyun  * subject to backwards-compatibility constraints.
35*4882a593Smuzhiyun  *
36*4882a593Smuzhiyun  * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
37*4882a593Smuzhiyun  * compatibility Keep fields aligned to their size
38*4882a593Smuzhiyun  */
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define DRM_VIRTGPU_MAP         0x01
41*4882a593Smuzhiyun #define DRM_VIRTGPU_EXECBUFFER  0x02
42*4882a593Smuzhiyun #define DRM_VIRTGPU_GETPARAM    0x03
43*4882a593Smuzhiyun #define DRM_VIRTGPU_RESOURCE_CREATE 0x04
44*4882a593Smuzhiyun #define DRM_VIRTGPU_RESOURCE_INFO     0x05
45*4882a593Smuzhiyun #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
46*4882a593Smuzhiyun #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
47*4882a593Smuzhiyun #define DRM_VIRTGPU_WAIT     0x08
48*4882a593Smuzhiyun #define DRM_VIRTGPU_GET_CAPS  0x09
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define VIRTGPU_EXECBUF_FENCE_FD_IN	0x01
51*4882a593Smuzhiyun #define VIRTGPU_EXECBUF_FENCE_FD_OUT	0x02
52*4882a593Smuzhiyun #define VIRTGPU_EXECBUF_FLAGS  (\
53*4882a593Smuzhiyun 		VIRTGPU_EXECBUF_FENCE_FD_IN |\
54*4882a593Smuzhiyun 		VIRTGPU_EXECBUF_FENCE_FD_OUT |\
55*4882a593Smuzhiyun 		0)
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun struct drm_virtgpu_map {
58*4882a593Smuzhiyun 	__u64 offset; /* use for mmap system call */
59*4882a593Smuzhiyun 	__u32 handle;
60*4882a593Smuzhiyun 	__u32 pad;
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun struct drm_virtgpu_execbuffer {
64*4882a593Smuzhiyun 	__u32 flags;
65*4882a593Smuzhiyun 	__u32 size;
66*4882a593Smuzhiyun 	__u64 command; /* void* */
67*4882a593Smuzhiyun 	__u64 bo_handles;
68*4882a593Smuzhiyun 	__u32 num_bo_handles;
69*4882a593Smuzhiyun 	__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
73*4882a593Smuzhiyun #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun struct drm_virtgpu_getparam {
76*4882a593Smuzhiyun 	__u64 param;
77*4882a593Smuzhiyun 	__u64 value;
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* NO_BO flags? NO resource flag? */
81*4882a593Smuzhiyun /* resource flag for y_0_top */
82*4882a593Smuzhiyun struct drm_virtgpu_resource_create {
83*4882a593Smuzhiyun 	__u32 target;
84*4882a593Smuzhiyun 	__u32 format;
85*4882a593Smuzhiyun 	__u32 bind;
86*4882a593Smuzhiyun 	__u32 width;
87*4882a593Smuzhiyun 	__u32 height;
88*4882a593Smuzhiyun 	__u32 depth;
89*4882a593Smuzhiyun 	__u32 array_size;
90*4882a593Smuzhiyun 	__u32 last_level;
91*4882a593Smuzhiyun 	__u32 nr_samples;
92*4882a593Smuzhiyun 	__u32 flags;
93*4882a593Smuzhiyun 	__u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
94*4882a593Smuzhiyun 	__u32 res_handle;  /* returned by kernel */
95*4882a593Smuzhiyun 	__u32 size;        /* validate transfer in the host */
96*4882a593Smuzhiyun 	__u32 stride;      /* validate transfer in the host */
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun struct drm_virtgpu_resource_info {
100*4882a593Smuzhiyun 	__u32 bo_handle;
101*4882a593Smuzhiyun 	__u32 res_handle;
102*4882a593Smuzhiyun 	__u32 size;
103*4882a593Smuzhiyun 	__u32 stride;
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun struct drm_virtgpu_3d_box {
107*4882a593Smuzhiyun 	__u32 x;
108*4882a593Smuzhiyun 	__u32 y;
109*4882a593Smuzhiyun 	__u32 z;
110*4882a593Smuzhiyun 	__u32 w;
111*4882a593Smuzhiyun 	__u32 h;
112*4882a593Smuzhiyun 	__u32 d;
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun struct drm_virtgpu_3d_transfer_to_host {
116*4882a593Smuzhiyun 	__u32 bo_handle;
117*4882a593Smuzhiyun 	struct drm_virtgpu_3d_box box;
118*4882a593Smuzhiyun 	__u32 level;
119*4882a593Smuzhiyun 	__u32 offset;
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun struct drm_virtgpu_3d_transfer_from_host {
123*4882a593Smuzhiyun 	__u32 bo_handle;
124*4882a593Smuzhiyun 	struct drm_virtgpu_3d_box box;
125*4882a593Smuzhiyun 	__u32 level;
126*4882a593Smuzhiyun 	__u32 offset;
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun #define VIRTGPU_WAIT_NOWAIT 1 /* like it */
130*4882a593Smuzhiyun struct drm_virtgpu_3d_wait {
131*4882a593Smuzhiyun 	__u32 handle; /* 0 is an invalid handle */
132*4882a593Smuzhiyun 	__u32 flags;
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun struct drm_virtgpu_get_caps {
136*4882a593Smuzhiyun 	__u32 cap_set_id;
137*4882a593Smuzhiyun 	__u32 cap_set_ver;
138*4882a593Smuzhiyun 	__u64 addr;
139*4882a593Smuzhiyun 	__u32 size;
140*4882a593Smuzhiyun 	__u32 pad;
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun #define DRM_IOCTL_VIRTGPU_MAP \
144*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun #define DRM_IOCTL_VIRTGPU_EXECBUFFER \
147*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
148*4882a593Smuzhiyun 		struct drm_virtgpu_execbuffer)
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun #define DRM_IOCTL_VIRTGPU_GETPARAM \
151*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
152*4882a593Smuzhiyun 		struct drm_virtgpu_getparam)
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE			\
155*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE,	\
156*4882a593Smuzhiyun 		struct drm_virtgpu_resource_create)
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
159*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
160*4882a593Smuzhiyun 		 struct drm_virtgpu_resource_info)
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
163*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST,	\
164*4882a593Smuzhiyun 		struct drm_virtgpu_3d_transfer_from_host)
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
167*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST,	\
168*4882a593Smuzhiyun 		struct drm_virtgpu_3d_transfer_to_host)
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun #define DRM_IOCTL_VIRTGPU_WAIT				\
171*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT,	\
172*4882a593Smuzhiyun 		struct drm_virtgpu_3d_wait)
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun #define DRM_IOCTL_VIRTGPU_GET_CAPS \
175*4882a593Smuzhiyun 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
176*4882a593Smuzhiyun 	struct drm_virtgpu_get_caps)
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun #if defined(__cplusplus)
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun #endif
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun #endif
183