xref: /OK3568_Linux_fs/kernel/include/uapi/drm/via_drm.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3*4882a593Smuzhiyun  * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
6*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
7*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
8*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sub license,
9*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
10*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * The above copyright notice and this permission notice (including the
13*4882a593Smuzhiyun  * next paragraph) shall be included in all copies or substantial portions
14*4882a593Smuzhiyun  * of the Software.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19*4882a593Smuzhiyun  * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22*4882a593Smuzhiyun  * DEALINGS IN THE SOFTWARE.
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun #ifndef _VIA_DRM_H_
25*4882a593Smuzhiyun #define _VIA_DRM_H_
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "drm.h"
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #if defined(__cplusplus)
30*4882a593Smuzhiyun extern "C" {
31*4882a593Smuzhiyun #endif
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* WARNING: These defines must be the same as what the Xserver uses.
34*4882a593Smuzhiyun  * if you change them, you must change the defines in the Xserver.
35*4882a593Smuzhiyun  */
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #ifndef _VIA_DEFINES_
38*4882a593Smuzhiyun #define _VIA_DEFINES_
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define VIA_NR_SAREA_CLIPRECTS		8
42*4882a593Smuzhiyun #define VIA_NR_XVMC_PORTS               10
43*4882a593Smuzhiyun #define VIA_NR_XVMC_LOCKS               5
44*4882a593Smuzhiyun #define VIA_MAX_CACHELINE_SIZE          64
45*4882a593Smuzhiyun #define XVMCLOCKPTR(saPriv,lockNo)					\
46*4882a593Smuzhiyun 	((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
47*4882a593Smuzhiyun 				      (VIA_MAX_CACHELINE_SIZE - 1)) &	\
48*4882a593Smuzhiyun 				     ~(VIA_MAX_CACHELINE_SIZE - 1)) +	\
49*4882a593Smuzhiyun 				    VIA_MAX_CACHELINE_SIZE*(lockNo)))
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* Each region is a minimum of 64k, and there are at most 64 of them.
52*4882a593Smuzhiyun  */
53*4882a593Smuzhiyun #define VIA_NR_TEX_REGIONS 64
54*4882a593Smuzhiyun #define VIA_LOG_MIN_TEX_REGION_SIZE 16
55*4882a593Smuzhiyun #endif
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define VIA_UPLOAD_TEX0IMAGE  0x1	/* handled clientside */
58*4882a593Smuzhiyun #define VIA_UPLOAD_TEX1IMAGE  0x2	/* handled clientside */
59*4882a593Smuzhiyun #define VIA_UPLOAD_CTX        0x4
60*4882a593Smuzhiyun #define VIA_UPLOAD_BUFFERS    0x8
61*4882a593Smuzhiyun #define VIA_UPLOAD_TEX0       0x10
62*4882a593Smuzhiyun #define VIA_UPLOAD_TEX1       0x20
63*4882a593Smuzhiyun #define VIA_UPLOAD_CLIPRECTS  0x40
64*4882a593Smuzhiyun #define VIA_UPLOAD_ALL        0xff
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /* VIA specific ioctls */
67*4882a593Smuzhiyun #define DRM_VIA_ALLOCMEM	0x00
68*4882a593Smuzhiyun #define DRM_VIA_FREEMEM	        0x01
69*4882a593Smuzhiyun #define DRM_VIA_AGP_INIT	0x02
70*4882a593Smuzhiyun #define DRM_VIA_FB_INIT	        0x03
71*4882a593Smuzhiyun #define DRM_VIA_MAP_INIT	0x04
72*4882a593Smuzhiyun #define DRM_VIA_DEC_FUTEX       0x05
73*4882a593Smuzhiyun #define NOT_USED
74*4882a593Smuzhiyun #define DRM_VIA_DMA_INIT	0x07
75*4882a593Smuzhiyun #define DRM_VIA_CMDBUFFER	0x08
76*4882a593Smuzhiyun #define DRM_VIA_FLUSH	        0x09
77*4882a593Smuzhiyun #define DRM_VIA_PCICMD	        0x0a
78*4882a593Smuzhiyun #define DRM_VIA_CMDBUF_SIZE	0x0b
79*4882a593Smuzhiyun #define NOT_USED
80*4882a593Smuzhiyun #define DRM_VIA_WAIT_IRQ        0x0d
81*4882a593Smuzhiyun #define DRM_VIA_DMA_BLIT        0x0e
82*4882a593Smuzhiyun #define DRM_VIA_BLIT_SYNC       0x0f
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #define DRM_IOCTL_VIA_ALLOCMEM	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
85*4882a593Smuzhiyun #define DRM_IOCTL_VIA_FREEMEM	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
86*4882a593Smuzhiyun #define DRM_IOCTL_VIA_AGP_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
87*4882a593Smuzhiyun #define DRM_IOCTL_VIA_FB_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
88*4882a593Smuzhiyun #define DRM_IOCTL_VIA_MAP_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
89*4882a593Smuzhiyun #define DRM_IOCTL_VIA_DEC_FUTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
90*4882a593Smuzhiyun #define DRM_IOCTL_VIA_DMA_INIT	  DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
91*4882a593Smuzhiyun #define DRM_IOCTL_VIA_CMDBUFFER	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
92*4882a593Smuzhiyun #define DRM_IOCTL_VIA_FLUSH	  DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
93*4882a593Smuzhiyun #define DRM_IOCTL_VIA_PCICMD	  DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
94*4882a593Smuzhiyun #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
95*4882a593Smuzhiyun 					    drm_via_cmdbuf_size_t)
96*4882a593Smuzhiyun #define DRM_IOCTL_VIA_WAIT_IRQ    DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
97*4882a593Smuzhiyun #define DRM_IOCTL_VIA_DMA_BLIT    DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
98*4882a593Smuzhiyun #define DRM_IOCTL_VIA_BLIT_SYNC   DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /* Indices into buf.Setup where various bits of state are mirrored per
101*4882a593Smuzhiyun  * context and per buffer.  These can be fired at the card as a unit,
102*4882a593Smuzhiyun  * or in a piecewise fashion as required.
103*4882a593Smuzhiyun  */
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun #define VIA_TEX_SETUP_SIZE 8
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /* Flags for clear ioctl
108*4882a593Smuzhiyun  */
109*4882a593Smuzhiyun #define VIA_FRONT   0x1
110*4882a593Smuzhiyun #define VIA_BACK    0x2
111*4882a593Smuzhiyun #define VIA_DEPTH   0x4
112*4882a593Smuzhiyun #define VIA_STENCIL 0x8
113*4882a593Smuzhiyun #define VIA_MEM_VIDEO   0	/* matches drm constant */
114*4882a593Smuzhiyun #define VIA_MEM_AGP     1	/* matches drm constant */
115*4882a593Smuzhiyun #define VIA_MEM_SYSTEM  2
116*4882a593Smuzhiyun #define VIA_MEM_MIXED   3
117*4882a593Smuzhiyun #define VIA_MEM_UNKNOWN 4
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun typedef struct {
120*4882a593Smuzhiyun 	__u32 offset;
121*4882a593Smuzhiyun 	__u32 size;
122*4882a593Smuzhiyun } drm_via_agp_t;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun typedef struct {
125*4882a593Smuzhiyun 	__u32 offset;
126*4882a593Smuzhiyun 	__u32 size;
127*4882a593Smuzhiyun } drm_via_fb_t;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun typedef struct {
130*4882a593Smuzhiyun 	__u32 context;
131*4882a593Smuzhiyun 	__u32 type;
132*4882a593Smuzhiyun 	__u32 size;
133*4882a593Smuzhiyun 	unsigned long index;
134*4882a593Smuzhiyun 	unsigned long offset;
135*4882a593Smuzhiyun } drm_via_mem_t;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun typedef struct _drm_via_init {
138*4882a593Smuzhiyun 	enum {
139*4882a593Smuzhiyun 		VIA_INIT_MAP = 0x01,
140*4882a593Smuzhiyun 		VIA_CLEANUP_MAP = 0x02
141*4882a593Smuzhiyun 	} func;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	unsigned long sarea_priv_offset;
144*4882a593Smuzhiyun 	unsigned long fb_offset;
145*4882a593Smuzhiyun 	unsigned long mmio_offset;
146*4882a593Smuzhiyun 	unsigned long agpAddr;
147*4882a593Smuzhiyun } drm_via_init_t;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun typedef struct _drm_via_futex {
150*4882a593Smuzhiyun 	enum {
151*4882a593Smuzhiyun 		VIA_FUTEX_WAIT = 0x00,
152*4882a593Smuzhiyun 		VIA_FUTEX_WAKE = 0X01
153*4882a593Smuzhiyun 	} func;
154*4882a593Smuzhiyun 	__u32 ms;
155*4882a593Smuzhiyun 	__u32 lock;
156*4882a593Smuzhiyun 	__u32 val;
157*4882a593Smuzhiyun } drm_via_futex_t;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun typedef struct _drm_via_dma_init {
160*4882a593Smuzhiyun 	enum {
161*4882a593Smuzhiyun 		VIA_INIT_DMA = 0x01,
162*4882a593Smuzhiyun 		VIA_CLEANUP_DMA = 0x02,
163*4882a593Smuzhiyun 		VIA_DMA_INITIALIZED = 0x03
164*4882a593Smuzhiyun 	} func;
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	unsigned long offset;
167*4882a593Smuzhiyun 	unsigned long size;
168*4882a593Smuzhiyun 	unsigned long reg_pause_addr;
169*4882a593Smuzhiyun } drm_via_dma_init_t;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun typedef struct _drm_via_cmdbuffer {
172*4882a593Smuzhiyun 	char __user *buf;
173*4882a593Smuzhiyun 	unsigned long size;
174*4882a593Smuzhiyun } drm_via_cmdbuffer_t;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun /* Warning: If you change the SAREA structure you must change the Xserver
177*4882a593Smuzhiyun  * structure as well */
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun typedef struct _drm_via_tex_region {
180*4882a593Smuzhiyun 	unsigned char next, prev;	/* indices to form a circular LRU  */
181*4882a593Smuzhiyun 	unsigned char inUse;	/* owned by a client, or free? */
182*4882a593Smuzhiyun 	int age;		/* tracked by clients to update local LRU's */
183*4882a593Smuzhiyun } drm_via_tex_region_t;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun typedef struct _drm_via_sarea {
186*4882a593Smuzhiyun 	unsigned int dirty;
187*4882a593Smuzhiyun 	unsigned int nbox;
188*4882a593Smuzhiyun 	struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
189*4882a593Smuzhiyun 	drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
190*4882a593Smuzhiyun 	int texAge;		/* last time texture was uploaded */
191*4882a593Smuzhiyun 	int ctxOwner;		/* last context to upload state */
192*4882a593Smuzhiyun 	int vertexPrim;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	/*
195*4882a593Smuzhiyun 	 * Below is for XvMC.
196*4882a593Smuzhiyun 	 * We want the lock integers alone on, and aligned to, a cache line.
197*4882a593Smuzhiyun 	 * Therefore this somewhat strange construct.
198*4882a593Smuzhiyun 	 */
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
203*4882a593Smuzhiyun 	unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
204*4882a593Smuzhiyun 	unsigned int XvMCCtxNoGrabbed;	/* Last context to hold decoder */
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 	/* Used by the 3d driver only at this point, for pageflipping:
207*4882a593Smuzhiyun 	 */
208*4882a593Smuzhiyun 	unsigned int pfCurrentOffset;
209*4882a593Smuzhiyun } drm_via_sarea_t;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun typedef struct _drm_via_cmdbuf_size {
212*4882a593Smuzhiyun 	enum {
213*4882a593Smuzhiyun 		VIA_CMDBUF_SPACE = 0x01,
214*4882a593Smuzhiyun 		VIA_CMDBUF_LAG = 0x02
215*4882a593Smuzhiyun 	} func;
216*4882a593Smuzhiyun 	int wait;
217*4882a593Smuzhiyun 	__u32 size;
218*4882a593Smuzhiyun } drm_via_cmdbuf_size_t;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun typedef enum {
221*4882a593Smuzhiyun 	VIA_IRQ_ABSOLUTE = 0x0,
222*4882a593Smuzhiyun 	VIA_IRQ_RELATIVE = 0x1,
223*4882a593Smuzhiyun 	VIA_IRQ_SIGNAL = 0x10000000,
224*4882a593Smuzhiyun 	VIA_IRQ_FORCE_SEQUENCE = 0x20000000
225*4882a593Smuzhiyun } via_irq_seq_type_t;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun #define VIA_IRQ_FLAGS_MASK 0xF0000000
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun enum drm_via_irqs {
230*4882a593Smuzhiyun 	drm_via_irq_hqv0 = 0,
231*4882a593Smuzhiyun 	drm_via_irq_hqv1,
232*4882a593Smuzhiyun 	drm_via_irq_dma0_dd,
233*4882a593Smuzhiyun 	drm_via_irq_dma0_td,
234*4882a593Smuzhiyun 	drm_via_irq_dma1_dd,
235*4882a593Smuzhiyun 	drm_via_irq_dma1_td,
236*4882a593Smuzhiyun 	drm_via_irq_num
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun struct drm_via_wait_irq_request {
240*4882a593Smuzhiyun 	unsigned irq;
241*4882a593Smuzhiyun 	via_irq_seq_type_t type;
242*4882a593Smuzhiyun 	__u32 sequence;
243*4882a593Smuzhiyun 	__u32 signal;
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun typedef union drm_via_irqwait {
247*4882a593Smuzhiyun 	struct drm_via_wait_irq_request request;
248*4882a593Smuzhiyun 	struct drm_wait_vblank_reply reply;
249*4882a593Smuzhiyun } drm_via_irqwait_t;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun typedef struct drm_via_blitsync {
252*4882a593Smuzhiyun 	__u32 sync_handle;
253*4882a593Smuzhiyun 	unsigned engine;
254*4882a593Smuzhiyun } drm_via_blitsync_t;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun /* - * Below,"flags" is currently unused but will be used for possible future
257*4882a593Smuzhiyun  * extensions like kernel space bounce buffers for bad alignments and
258*4882a593Smuzhiyun  * blit engine busy-wait polling for better latency in the absence of
259*4882a593Smuzhiyun  * interrupts.
260*4882a593Smuzhiyun  */
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun typedef struct drm_via_dmablit {
263*4882a593Smuzhiyun 	__u32 num_lines;
264*4882a593Smuzhiyun 	__u32 line_length;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	__u32 fb_addr;
267*4882a593Smuzhiyun 	__u32 fb_stride;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	unsigned char *mem_addr;
270*4882a593Smuzhiyun 	__u32 mem_stride;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	__u32 flags;
273*4882a593Smuzhiyun 	int to_fb;
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	drm_via_blitsync_t sync;
276*4882a593Smuzhiyun } drm_via_dmablit_t;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun #if defined(__cplusplus)
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun #endif
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun #endif				/* _VIA_DRM_H_ */
283