xref: /OK3568_Linux_fs/kernel/include/uapi/drm/tegra_drm.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun  * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*4882a593Smuzhiyun  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun  * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun  */
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #ifndef _UAPI_TEGRA_DRM_H_
24*4882a593Smuzhiyun #define _UAPI_TEGRA_DRM_H_
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include "drm.h"
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #if defined(__cplusplus)
29*4882a593Smuzhiyun extern "C" {
30*4882a593Smuzhiyun #endif
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
33*4882a593Smuzhiyun #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /**
36*4882a593Smuzhiyun  * struct drm_tegra_gem_create - parameters for the GEM object creation IOCTL
37*4882a593Smuzhiyun  */
38*4882a593Smuzhiyun struct drm_tegra_gem_create {
39*4882a593Smuzhiyun 	/**
40*4882a593Smuzhiyun 	 * @size:
41*4882a593Smuzhiyun 	 *
42*4882a593Smuzhiyun 	 * The size, in bytes, of the buffer object to be created.
43*4882a593Smuzhiyun 	 */
44*4882a593Smuzhiyun 	__u64 size;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	/**
47*4882a593Smuzhiyun 	 * @flags:
48*4882a593Smuzhiyun 	 *
49*4882a593Smuzhiyun 	 * A bitmask of flags that influence the creation of GEM objects:
50*4882a593Smuzhiyun 	 *
51*4882a593Smuzhiyun 	 * DRM_TEGRA_GEM_CREATE_TILED
52*4882a593Smuzhiyun 	 *   Use the 16x16 tiling format for this buffer.
53*4882a593Smuzhiyun 	 *
54*4882a593Smuzhiyun 	 * DRM_TEGRA_GEM_CREATE_BOTTOM_UP
55*4882a593Smuzhiyun 	 *   The buffer has a bottom-up layout.
56*4882a593Smuzhiyun 	 */
57*4882a593Smuzhiyun 	__u32 flags;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	/**
60*4882a593Smuzhiyun 	 * @handle:
61*4882a593Smuzhiyun 	 *
62*4882a593Smuzhiyun 	 * The handle of the created GEM object. Set by the kernel upon
63*4882a593Smuzhiyun 	 * successful completion of the IOCTL.
64*4882a593Smuzhiyun 	 */
65*4882a593Smuzhiyun 	__u32 handle;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /**
69*4882a593Smuzhiyun  * struct drm_tegra_gem_mmap - parameters for the GEM mmap IOCTL
70*4882a593Smuzhiyun  */
71*4882a593Smuzhiyun struct drm_tegra_gem_mmap {
72*4882a593Smuzhiyun 	/**
73*4882a593Smuzhiyun 	 * @handle:
74*4882a593Smuzhiyun 	 *
75*4882a593Smuzhiyun 	 * Handle of the GEM object to obtain an mmap offset for.
76*4882a593Smuzhiyun 	 */
77*4882a593Smuzhiyun 	__u32 handle;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	/**
80*4882a593Smuzhiyun 	 * @pad:
81*4882a593Smuzhiyun 	 *
82*4882a593Smuzhiyun 	 * Structure padding that may be used in the future. Must be 0.
83*4882a593Smuzhiyun 	 */
84*4882a593Smuzhiyun 	__u32 pad;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	/**
87*4882a593Smuzhiyun 	 * @offset:
88*4882a593Smuzhiyun 	 *
89*4882a593Smuzhiyun 	 * The mmap offset for the given GEM object. Set by the kernel upon
90*4882a593Smuzhiyun 	 * successful completion of the IOCTL.
91*4882a593Smuzhiyun 	 */
92*4882a593Smuzhiyun 	__u64 offset;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun /**
96*4882a593Smuzhiyun  * struct drm_tegra_syncpt_read - parameters for the read syncpoint IOCTL
97*4882a593Smuzhiyun  */
98*4882a593Smuzhiyun struct drm_tegra_syncpt_read {
99*4882a593Smuzhiyun 	/**
100*4882a593Smuzhiyun 	 * @id:
101*4882a593Smuzhiyun 	 *
102*4882a593Smuzhiyun 	 * ID of the syncpoint to read the current value from.
103*4882a593Smuzhiyun 	 */
104*4882a593Smuzhiyun 	__u32 id;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	/**
107*4882a593Smuzhiyun 	 * @value:
108*4882a593Smuzhiyun 	 *
109*4882a593Smuzhiyun 	 * The current syncpoint value. Set by the kernel upon successful
110*4882a593Smuzhiyun 	 * completion of the IOCTL.
111*4882a593Smuzhiyun 	 */
112*4882a593Smuzhiyun 	__u32 value;
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /**
116*4882a593Smuzhiyun  * struct drm_tegra_syncpt_incr - parameters for the increment syncpoint IOCTL
117*4882a593Smuzhiyun  */
118*4882a593Smuzhiyun struct drm_tegra_syncpt_incr {
119*4882a593Smuzhiyun 	/**
120*4882a593Smuzhiyun 	 * @id:
121*4882a593Smuzhiyun 	 *
122*4882a593Smuzhiyun 	 * ID of the syncpoint to increment.
123*4882a593Smuzhiyun 	 */
124*4882a593Smuzhiyun 	__u32 id;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	/**
127*4882a593Smuzhiyun 	 * @pad:
128*4882a593Smuzhiyun 	 *
129*4882a593Smuzhiyun 	 * Structure padding that may be used in the future. Must be 0.
130*4882a593Smuzhiyun 	 */
131*4882a593Smuzhiyun 	__u32 pad;
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun /**
135*4882a593Smuzhiyun  * struct drm_tegra_syncpt_wait - parameters for the wait syncpoint IOCTL
136*4882a593Smuzhiyun  */
137*4882a593Smuzhiyun struct drm_tegra_syncpt_wait {
138*4882a593Smuzhiyun 	/**
139*4882a593Smuzhiyun 	 * @id:
140*4882a593Smuzhiyun 	 *
141*4882a593Smuzhiyun 	 * ID of the syncpoint to wait on.
142*4882a593Smuzhiyun 	 */
143*4882a593Smuzhiyun 	__u32 id;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun 	/**
146*4882a593Smuzhiyun 	 * @thresh:
147*4882a593Smuzhiyun 	 *
148*4882a593Smuzhiyun 	 * Threshold value for which to wait.
149*4882a593Smuzhiyun 	 */
150*4882a593Smuzhiyun 	__u32 thresh;
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	/**
153*4882a593Smuzhiyun 	 * @timeout:
154*4882a593Smuzhiyun 	 *
155*4882a593Smuzhiyun 	 * Timeout, in milliseconds, to wait.
156*4882a593Smuzhiyun 	 */
157*4882a593Smuzhiyun 	__u32 timeout;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	/**
160*4882a593Smuzhiyun 	 * @value:
161*4882a593Smuzhiyun 	 *
162*4882a593Smuzhiyun 	 * The new syncpoint value after the wait. Set by the kernel upon
163*4882a593Smuzhiyun 	 * successful completion of the IOCTL.
164*4882a593Smuzhiyun 	 */
165*4882a593Smuzhiyun 	__u32 value;
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun #define DRM_TEGRA_NO_TIMEOUT	(0xffffffff)
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /**
171*4882a593Smuzhiyun  * struct drm_tegra_open_channel - parameters for the open channel IOCTL
172*4882a593Smuzhiyun  */
173*4882a593Smuzhiyun struct drm_tegra_open_channel {
174*4882a593Smuzhiyun 	/**
175*4882a593Smuzhiyun 	 * @client:
176*4882a593Smuzhiyun 	 *
177*4882a593Smuzhiyun 	 * The client ID for this channel.
178*4882a593Smuzhiyun 	 */
179*4882a593Smuzhiyun 	__u32 client;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	/**
182*4882a593Smuzhiyun 	 * @pad:
183*4882a593Smuzhiyun 	 *
184*4882a593Smuzhiyun 	 * Structure padding that may be used in the future. Must be 0.
185*4882a593Smuzhiyun 	 */
186*4882a593Smuzhiyun 	__u32 pad;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	/**
189*4882a593Smuzhiyun 	 * @context:
190*4882a593Smuzhiyun 	 *
191*4882a593Smuzhiyun 	 * The application context of this channel. Set by the kernel upon
192*4882a593Smuzhiyun 	 * successful completion of the IOCTL. This context needs to be passed
193*4882a593Smuzhiyun 	 * to the DRM_TEGRA_CHANNEL_CLOSE or the DRM_TEGRA_SUBMIT IOCTLs.
194*4882a593Smuzhiyun 	 */
195*4882a593Smuzhiyun 	__u64 context;
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun /**
199*4882a593Smuzhiyun  * struct drm_tegra_close_channel - parameters for the close channel IOCTL
200*4882a593Smuzhiyun  */
201*4882a593Smuzhiyun struct drm_tegra_close_channel {
202*4882a593Smuzhiyun 	/**
203*4882a593Smuzhiyun 	 * @context:
204*4882a593Smuzhiyun 	 *
205*4882a593Smuzhiyun 	 * The application context of this channel. This is obtained from the
206*4882a593Smuzhiyun 	 * DRM_TEGRA_OPEN_CHANNEL IOCTL.
207*4882a593Smuzhiyun 	 */
208*4882a593Smuzhiyun 	__u64 context;
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun /**
212*4882a593Smuzhiyun  * struct drm_tegra_get_syncpt - parameters for the get syncpoint IOCTL
213*4882a593Smuzhiyun  */
214*4882a593Smuzhiyun struct drm_tegra_get_syncpt {
215*4882a593Smuzhiyun 	/**
216*4882a593Smuzhiyun 	 * @context:
217*4882a593Smuzhiyun 	 *
218*4882a593Smuzhiyun 	 * The application context identifying the channel for which to obtain
219*4882a593Smuzhiyun 	 * the syncpoint ID.
220*4882a593Smuzhiyun 	 */
221*4882a593Smuzhiyun 	__u64 context;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	/**
224*4882a593Smuzhiyun 	 * @index:
225*4882a593Smuzhiyun 	 *
226*4882a593Smuzhiyun 	 * Index of the client syncpoint for which to obtain the ID.
227*4882a593Smuzhiyun 	 */
228*4882a593Smuzhiyun 	__u32 index;
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun 	/**
231*4882a593Smuzhiyun 	 * @id:
232*4882a593Smuzhiyun 	 *
233*4882a593Smuzhiyun 	 * The ID of the given syncpoint. Set by the kernel upon successful
234*4882a593Smuzhiyun 	 * completion of the IOCTL.
235*4882a593Smuzhiyun 	 */
236*4882a593Smuzhiyun 	__u32 id;
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun /**
240*4882a593Smuzhiyun  * struct drm_tegra_get_syncpt_base - parameters for the get wait base IOCTL
241*4882a593Smuzhiyun  */
242*4882a593Smuzhiyun struct drm_tegra_get_syncpt_base {
243*4882a593Smuzhiyun 	/**
244*4882a593Smuzhiyun 	 * @context:
245*4882a593Smuzhiyun 	 *
246*4882a593Smuzhiyun 	 * The application context identifying for which channel to obtain the
247*4882a593Smuzhiyun 	 * wait base.
248*4882a593Smuzhiyun 	 */
249*4882a593Smuzhiyun 	__u64 context;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	/**
252*4882a593Smuzhiyun 	 * @syncpt:
253*4882a593Smuzhiyun 	 *
254*4882a593Smuzhiyun 	 * ID of the syncpoint for which to obtain the wait base.
255*4882a593Smuzhiyun 	 */
256*4882a593Smuzhiyun 	__u32 syncpt;
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun 	/**
259*4882a593Smuzhiyun 	 * @id:
260*4882a593Smuzhiyun 	 *
261*4882a593Smuzhiyun 	 * The ID of the wait base corresponding to the client syncpoint. Set
262*4882a593Smuzhiyun 	 * by the kernel upon successful completion of the IOCTL.
263*4882a593Smuzhiyun 	 */
264*4882a593Smuzhiyun 	__u32 id;
265*4882a593Smuzhiyun };
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun /**
268*4882a593Smuzhiyun  * struct drm_tegra_syncpt - syncpoint increment operation
269*4882a593Smuzhiyun  */
270*4882a593Smuzhiyun struct drm_tegra_syncpt {
271*4882a593Smuzhiyun 	/**
272*4882a593Smuzhiyun 	 * @id:
273*4882a593Smuzhiyun 	 *
274*4882a593Smuzhiyun 	 * ID of the syncpoint to operate on.
275*4882a593Smuzhiyun 	 */
276*4882a593Smuzhiyun 	__u32 id;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	/**
279*4882a593Smuzhiyun 	 * @incrs:
280*4882a593Smuzhiyun 	 *
281*4882a593Smuzhiyun 	 * Number of increments to perform for the syncpoint.
282*4882a593Smuzhiyun 	 */
283*4882a593Smuzhiyun 	__u32 incrs;
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun /**
287*4882a593Smuzhiyun  * struct drm_tegra_cmdbuf - structure describing a command buffer
288*4882a593Smuzhiyun  */
289*4882a593Smuzhiyun struct drm_tegra_cmdbuf {
290*4882a593Smuzhiyun 	/**
291*4882a593Smuzhiyun 	 * @handle:
292*4882a593Smuzhiyun 	 *
293*4882a593Smuzhiyun 	 * Handle to a GEM object containing the command buffer.
294*4882a593Smuzhiyun 	 */
295*4882a593Smuzhiyun 	__u32 handle;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	/**
298*4882a593Smuzhiyun 	 * @offset:
299*4882a593Smuzhiyun 	 *
300*4882a593Smuzhiyun 	 * Offset, in bytes, into the GEM object identified by @handle at
301*4882a593Smuzhiyun 	 * which the command buffer starts.
302*4882a593Smuzhiyun 	 */
303*4882a593Smuzhiyun 	__u32 offset;
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	/**
306*4882a593Smuzhiyun 	 * @words:
307*4882a593Smuzhiyun 	 *
308*4882a593Smuzhiyun 	 * Number of 32-bit words in this command buffer.
309*4882a593Smuzhiyun 	 */
310*4882a593Smuzhiyun 	__u32 words;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	/**
313*4882a593Smuzhiyun 	 * @pad:
314*4882a593Smuzhiyun 	 *
315*4882a593Smuzhiyun 	 * Structure padding that may be used in the future. Must be 0.
316*4882a593Smuzhiyun 	 */
317*4882a593Smuzhiyun 	__u32 pad;
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun /**
321*4882a593Smuzhiyun  * struct drm_tegra_reloc - GEM object relocation structure
322*4882a593Smuzhiyun  */
323*4882a593Smuzhiyun struct drm_tegra_reloc {
324*4882a593Smuzhiyun 	struct {
325*4882a593Smuzhiyun 		/**
326*4882a593Smuzhiyun 		 * @cmdbuf.handle:
327*4882a593Smuzhiyun 		 *
328*4882a593Smuzhiyun 		 * Handle to the GEM object containing the command buffer for
329*4882a593Smuzhiyun 		 * which to perform this GEM object relocation.
330*4882a593Smuzhiyun 		 */
331*4882a593Smuzhiyun 		__u32 handle;
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 		/**
334*4882a593Smuzhiyun 		 * @cmdbuf.offset:
335*4882a593Smuzhiyun 		 *
336*4882a593Smuzhiyun 		 * Offset, in bytes, into the command buffer at which to
337*4882a593Smuzhiyun 		 * insert the relocated address.
338*4882a593Smuzhiyun 		 */
339*4882a593Smuzhiyun 		__u32 offset;
340*4882a593Smuzhiyun 	} cmdbuf;
341*4882a593Smuzhiyun 	struct {
342*4882a593Smuzhiyun 		/**
343*4882a593Smuzhiyun 		 * @target.handle:
344*4882a593Smuzhiyun 		 *
345*4882a593Smuzhiyun 		 * Handle to the GEM object to be relocated.
346*4882a593Smuzhiyun 		 */
347*4882a593Smuzhiyun 		__u32 handle;
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 		/**
350*4882a593Smuzhiyun 		 * @target.offset:
351*4882a593Smuzhiyun 		 *
352*4882a593Smuzhiyun 		 * Offset, in bytes, into the target GEM object at which the
353*4882a593Smuzhiyun 		 * relocated data starts.
354*4882a593Smuzhiyun 		 */
355*4882a593Smuzhiyun 		__u32 offset;
356*4882a593Smuzhiyun 	} target;
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	/**
359*4882a593Smuzhiyun 	 * @shift:
360*4882a593Smuzhiyun 	 *
361*4882a593Smuzhiyun 	 * The number of bits by which to shift relocated addresses.
362*4882a593Smuzhiyun 	 */
363*4882a593Smuzhiyun 	__u32 shift;
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	/**
366*4882a593Smuzhiyun 	 * @pad:
367*4882a593Smuzhiyun 	 *
368*4882a593Smuzhiyun 	 * Structure padding that may be used in the future. Must be 0.
369*4882a593Smuzhiyun 	 */
370*4882a593Smuzhiyun 	__u32 pad;
371*4882a593Smuzhiyun };
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun /**
374*4882a593Smuzhiyun  * struct drm_tegra_waitchk - wait check structure
375*4882a593Smuzhiyun  */
376*4882a593Smuzhiyun struct drm_tegra_waitchk {
377*4882a593Smuzhiyun 	/**
378*4882a593Smuzhiyun 	 * @handle:
379*4882a593Smuzhiyun 	 *
380*4882a593Smuzhiyun 	 * Handle to the GEM object containing a command stream on which to
381*4882a593Smuzhiyun 	 * perform the wait check.
382*4882a593Smuzhiyun 	 */
383*4882a593Smuzhiyun 	__u32 handle;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	/**
386*4882a593Smuzhiyun 	 * @offset:
387*4882a593Smuzhiyun 	 *
388*4882a593Smuzhiyun 	 * Offset, in bytes, of the location in the command stream to perform
389*4882a593Smuzhiyun 	 * the wait check on.
390*4882a593Smuzhiyun 	 */
391*4882a593Smuzhiyun 	__u32 offset;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	/**
394*4882a593Smuzhiyun 	 * @syncpt:
395*4882a593Smuzhiyun 	 *
396*4882a593Smuzhiyun 	 * ID of the syncpoint to wait check.
397*4882a593Smuzhiyun 	 */
398*4882a593Smuzhiyun 	__u32 syncpt;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	/**
401*4882a593Smuzhiyun 	 * @thresh:
402*4882a593Smuzhiyun 	 *
403*4882a593Smuzhiyun 	 * Threshold value for which to check.
404*4882a593Smuzhiyun 	 */
405*4882a593Smuzhiyun 	__u32 thresh;
406*4882a593Smuzhiyun };
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun /**
409*4882a593Smuzhiyun  * struct drm_tegra_submit - job submission structure
410*4882a593Smuzhiyun  */
411*4882a593Smuzhiyun struct drm_tegra_submit {
412*4882a593Smuzhiyun 	/**
413*4882a593Smuzhiyun 	 * @context:
414*4882a593Smuzhiyun 	 *
415*4882a593Smuzhiyun 	 * The application context identifying the channel to use for the
416*4882a593Smuzhiyun 	 * execution of this job.
417*4882a593Smuzhiyun 	 */
418*4882a593Smuzhiyun 	__u64 context;
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun 	/**
421*4882a593Smuzhiyun 	 * @num_syncpts:
422*4882a593Smuzhiyun 	 *
423*4882a593Smuzhiyun 	 * The number of syncpoints operated on by this job. This defines the
424*4882a593Smuzhiyun 	 * length of the array pointed to by @syncpts.
425*4882a593Smuzhiyun 	 */
426*4882a593Smuzhiyun 	__u32 num_syncpts;
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	/**
429*4882a593Smuzhiyun 	 * @num_cmdbufs:
430*4882a593Smuzhiyun 	 *
431*4882a593Smuzhiyun 	 * The number of command buffers to execute as part of this job. This
432*4882a593Smuzhiyun 	 * defines the length of the array pointed to by @cmdbufs.
433*4882a593Smuzhiyun 	 */
434*4882a593Smuzhiyun 	__u32 num_cmdbufs;
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	/**
437*4882a593Smuzhiyun 	 * @num_relocs:
438*4882a593Smuzhiyun 	 *
439*4882a593Smuzhiyun 	 * The number of relocations to perform before executing this job.
440*4882a593Smuzhiyun 	 * This defines the length of the array pointed to by @relocs.
441*4882a593Smuzhiyun 	 */
442*4882a593Smuzhiyun 	__u32 num_relocs;
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	/**
445*4882a593Smuzhiyun 	 * @num_waitchks:
446*4882a593Smuzhiyun 	 *
447*4882a593Smuzhiyun 	 * The number of wait checks to perform as part of this job. This
448*4882a593Smuzhiyun 	 * defines the length of the array pointed to by @waitchks.
449*4882a593Smuzhiyun 	 */
450*4882a593Smuzhiyun 	__u32 num_waitchks;
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	/**
453*4882a593Smuzhiyun 	 * @waitchk_mask:
454*4882a593Smuzhiyun 	 *
455*4882a593Smuzhiyun 	 * Bitmask of valid wait checks.
456*4882a593Smuzhiyun 	 */
457*4882a593Smuzhiyun 	__u32 waitchk_mask;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	/**
460*4882a593Smuzhiyun 	 * @timeout:
461*4882a593Smuzhiyun 	 *
462*4882a593Smuzhiyun 	 * Timeout, in milliseconds, before this job is cancelled.
463*4882a593Smuzhiyun 	 */
464*4882a593Smuzhiyun 	__u32 timeout;
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	/**
467*4882a593Smuzhiyun 	 * @syncpts:
468*4882a593Smuzhiyun 	 *
469*4882a593Smuzhiyun 	 * A pointer to an array of &struct drm_tegra_syncpt structures that
470*4882a593Smuzhiyun 	 * specify the syncpoint operations performed as part of this job.
471*4882a593Smuzhiyun 	 * The number of elements in the array must be equal to the value
472*4882a593Smuzhiyun 	 * given by @num_syncpts.
473*4882a593Smuzhiyun 	 */
474*4882a593Smuzhiyun 	__u64 syncpts;
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	/**
477*4882a593Smuzhiyun 	 * @cmdbufs:
478*4882a593Smuzhiyun 	 *
479*4882a593Smuzhiyun 	 * A pointer to an array of &struct drm_tegra_cmdbuf structures that
480*4882a593Smuzhiyun 	 * define the command buffers to execute as part of this job. The
481*4882a593Smuzhiyun 	 * number of elements in the array must be equal to the value given
482*4882a593Smuzhiyun 	 * by @num_syncpts.
483*4882a593Smuzhiyun 	 */
484*4882a593Smuzhiyun 	__u64 cmdbufs;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	/**
487*4882a593Smuzhiyun 	 * @relocs:
488*4882a593Smuzhiyun 	 *
489*4882a593Smuzhiyun 	 * A pointer to an array of &struct drm_tegra_reloc structures that
490*4882a593Smuzhiyun 	 * specify the relocations that need to be performed before executing
491*4882a593Smuzhiyun 	 * this job. The number of elements in the array must be equal to the
492*4882a593Smuzhiyun 	 * value given by @num_relocs.
493*4882a593Smuzhiyun 	 */
494*4882a593Smuzhiyun 	__u64 relocs;
495*4882a593Smuzhiyun 
496*4882a593Smuzhiyun 	/**
497*4882a593Smuzhiyun 	 * @waitchks:
498*4882a593Smuzhiyun 	 *
499*4882a593Smuzhiyun 	 * A pointer to an array of &struct drm_tegra_waitchk structures that
500*4882a593Smuzhiyun 	 * specify the wait checks to be performed while executing this job.
501*4882a593Smuzhiyun 	 * The number of elements in the array must be equal to the value
502*4882a593Smuzhiyun 	 * given by @num_waitchks.
503*4882a593Smuzhiyun 	 */
504*4882a593Smuzhiyun 	__u64 waitchks;
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun 	/**
507*4882a593Smuzhiyun 	 * @fence:
508*4882a593Smuzhiyun 	 *
509*4882a593Smuzhiyun 	 * The threshold of the syncpoint associated with this job after it
510*4882a593Smuzhiyun 	 * has been completed. Set by the kernel upon successful completion of
511*4882a593Smuzhiyun 	 * the IOCTL. This can be used with the DRM_TEGRA_SYNCPT_WAIT IOCTL to
512*4882a593Smuzhiyun 	 * wait for this job to be finished.
513*4882a593Smuzhiyun 	 */
514*4882a593Smuzhiyun 	__u32 fence;
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	/**
517*4882a593Smuzhiyun 	 * @reserved:
518*4882a593Smuzhiyun 	 *
519*4882a593Smuzhiyun 	 * This field is reserved for future use. Must be 0.
520*4882a593Smuzhiyun 	 */
521*4882a593Smuzhiyun 	__u32 reserved[5];
522*4882a593Smuzhiyun };
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
525*4882a593Smuzhiyun #define DRM_TEGRA_GEM_TILING_MODE_TILED 1
526*4882a593Smuzhiyun #define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun /**
529*4882a593Smuzhiyun  * struct drm_tegra_gem_set_tiling - parameters for the set tiling IOCTL
530*4882a593Smuzhiyun  */
531*4882a593Smuzhiyun struct drm_tegra_gem_set_tiling {
532*4882a593Smuzhiyun 	/**
533*4882a593Smuzhiyun 	 * @handle:
534*4882a593Smuzhiyun 	 *
535*4882a593Smuzhiyun 	 * Handle to the GEM object for which to set the tiling parameters.
536*4882a593Smuzhiyun 	 */
537*4882a593Smuzhiyun 	__u32 handle;
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	/**
540*4882a593Smuzhiyun 	 * @mode:
541*4882a593Smuzhiyun 	 *
542*4882a593Smuzhiyun 	 * The tiling mode to set. Must be one of:
543*4882a593Smuzhiyun 	 *
544*4882a593Smuzhiyun 	 * DRM_TEGRA_GEM_TILING_MODE_PITCH
545*4882a593Smuzhiyun 	 *   pitch linear format
546*4882a593Smuzhiyun 	 *
547*4882a593Smuzhiyun 	 * DRM_TEGRA_GEM_TILING_MODE_TILED
548*4882a593Smuzhiyun 	 *   16x16 tiling format
549*4882a593Smuzhiyun 	 *
550*4882a593Smuzhiyun 	 * DRM_TEGRA_GEM_TILING_MODE_BLOCK
551*4882a593Smuzhiyun 	 *   16Bx2 tiling format
552*4882a593Smuzhiyun 	 */
553*4882a593Smuzhiyun 	__u32 mode;
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	/**
556*4882a593Smuzhiyun 	 * @value:
557*4882a593Smuzhiyun 	 *
558*4882a593Smuzhiyun 	 * The value to set for the tiling mode parameter.
559*4882a593Smuzhiyun 	 */
560*4882a593Smuzhiyun 	__u32 value;
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 	/**
563*4882a593Smuzhiyun 	 * @pad:
564*4882a593Smuzhiyun 	 *
565*4882a593Smuzhiyun 	 * Structure padding that may be used in the future. Must be 0.
566*4882a593Smuzhiyun 	 */
567*4882a593Smuzhiyun 	__u32 pad;
568*4882a593Smuzhiyun };
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun /**
571*4882a593Smuzhiyun  * struct drm_tegra_gem_get_tiling - parameters for the get tiling IOCTL
572*4882a593Smuzhiyun  */
573*4882a593Smuzhiyun struct drm_tegra_gem_get_tiling {
574*4882a593Smuzhiyun 	/**
575*4882a593Smuzhiyun 	 * @handle:
576*4882a593Smuzhiyun 	 *
577*4882a593Smuzhiyun 	 * Handle to the GEM object for which to query the tiling parameters.
578*4882a593Smuzhiyun 	 */
579*4882a593Smuzhiyun 	__u32 handle;
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	/**
582*4882a593Smuzhiyun 	 * @mode:
583*4882a593Smuzhiyun 	 *
584*4882a593Smuzhiyun 	 * The tiling mode currently associated with the GEM object. Set by
585*4882a593Smuzhiyun 	 * the kernel upon successful completion of the IOCTL.
586*4882a593Smuzhiyun 	 */
587*4882a593Smuzhiyun 	__u32 mode;
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	/**
590*4882a593Smuzhiyun 	 * @value:
591*4882a593Smuzhiyun 	 *
592*4882a593Smuzhiyun 	 * The tiling mode parameter currently associated with the GEM object.
593*4882a593Smuzhiyun 	 * Set by the kernel upon successful completion of the IOCTL.
594*4882a593Smuzhiyun 	 */
595*4882a593Smuzhiyun 	__u32 value;
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	/**
598*4882a593Smuzhiyun 	 * @pad:
599*4882a593Smuzhiyun 	 *
600*4882a593Smuzhiyun 	 * Structure padding that may be used in the future. Must be 0.
601*4882a593Smuzhiyun 	 */
602*4882a593Smuzhiyun 	__u32 pad;
603*4882a593Smuzhiyun };
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun #define DRM_TEGRA_GEM_BOTTOM_UP		(1 << 0)
606*4882a593Smuzhiyun #define DRM_TEGRA_GEM_FLAGS		(DRM_TEGRA_GEM_BOTTOM_UP)
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun /**
609*4882a593Smuzhiyun  * struct drm_tegra_gem_set_flags - parameters for the set flags IOCTL
610*4882a593Smuzhiyun  */
611*4882a593Smuzhiyun struct drm_tegra_gem_set_flags {
612*4882a593Smuzhiyun 	/**
613*4882a593Smuzhiyun 	 * @handle:
614*4882a593Smuzhiyun 	 *
615*4882a593Smuzhiyun 	 * Handle to the GEM object for which to set the flags.
616*4882a593Smuzhiyun 	 */
617*4882a593Smuzhiyun 	__u32 handle;
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun 	/**
620*4882a593Smuzhiyun 	 * @flags:
621*4882a593Smuzhiyun 	 *
622*4882a593Smuzhiyun 	 * The flags to set for the GEM object.
623*4882a593Smuzhiyun 	 */
624*4882a593Smuzhiyun 	__u32 flags;
625*4882a593Smuzhiyun };
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun /**
628*4882a593Smuzhiyun  * struct drm_tegra_gem_get_flags - parameters for the get flags IOCTL
629*4882a593Smuzhiyun  */
630*4882a593Smuzhiyun struct drm_tegra_gem_get_flags {
631*4882a593Smuzhiyun 	/**
632*4882a593Smuzhiyun 	 * @handle:
633*4882a593Smuzhiyun 	 *
634*4882a593Smuzhiyun 	 * Handle to the GEM object for which to query the flags.
635*4882a593Smuzhiyun 	 */
636*4882a593Smuzhiyun 	__u32 handle;
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun 	/**
639*4882a593Smuzhiyun 	 * @flags:
640*4882a593Smuzhiyun 	 *
641*4882a593Smuzhiyun 	 * The flags currently associated with the GEM object. Set by the
642*4882a593Smuzhiyun 	 * kernel upon successful completion of the IOCTL.
643*4882a593Smuzhiyun 	 */
644*4882a593Smuzhiyun 	__u32 flags;
645*4882a593Smuzhiyun };
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun #define DRM_TEGRA_GEM_CREATE		0x00
648*4882a593Smuzhiyun #define DRM_TEGRA_GEM_MMAP		0x01
649*4882a593Smuzhiyun #define DRM_TEGRA_SYNCPT_READ		0x02
650*4882a593Smuzhiyun #define DRM_TEGRA_SYNCPT_INCR		0x03
651*4882a593Smuzhiyun #define DRM_TEGRA_SYNCPT_WAIT		0x04
652*4882a593Smuzhiyun #define DRM_TEGRA_OPEN_CHANNEL		0x05
653*4882a593Smuzhiyun #define DRM_TEGRA_CLOSE_CHANNEL		0x06
654*4882a593Smuzhiyun #define DRM_TEGRA_GET_SYNCPT		0x07
655*4882a593Smuzhiyun #define DRM_TEGRA_SUBMIT		0x08
656*4882a593Smuzhiyun #define DRM_TEGRA_GET_SYNCPT_BASE	0x09
657*4882a593Smuzhiyun #define DRM_TEGRA_GEM_SET_TILING	0x0a
658*4882a593Smuzhiyun #define DRM_TEGRA_GEM_GET_TILING	0x0b
659*4882a593Smuzhiyun #define DRM_TEGRA_GEM_SET_FLAGS		0x0c
660*4882a593Smuzhiyun #define DRM_TEGRA_GEM_GET_FLAGS		0x0d
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
663*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
664*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
665*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
666*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
667*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
668*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
669*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
670*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
671*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
672*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
673*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
674*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
675*4882a593Smuzhiyun #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
676*4882a593Smuzhiyun 
677*4882a593Smuzhiyun #if defined(__cplusplus)
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun #endif
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun #endif
682