1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (c) Fuzhou Rockchip Electronics Co.Ltd 4*4882a593Smuzhiyun * Authors: 5*4882a593Smuzhiyun * Mark Yao <yzq@rock-chips.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * base on exynos_drm.h 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 10*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the 11*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your 12*4882a593Smuzhiyun * option) any later version. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _UAPI_ROCKCHIP_DRM_H 16*4882a593Smuzhiyun #define _UAPI_ROCKCHIP_DRM_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifdef __KERNEL__ 19*4882a593Smuzhiyun #include <linux/types.h> 20*4882a593Smuzhiyun #else 21*4882a593Smuzhiyun #include <stdint.h> 22*4882a593Smuzhiyun #endif 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #include <drm/drm.h> 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Send vcnt event instead of blocking, 28*4882a593Smuzhiyun * like _DRM_VBLANK_EVENT 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define _DRM_ROCKCHIP_VCNT_EVENT 0x80000000 31*4882a593Smuzhiyun #define DRM_EVENT_ROCKCHIP_CRTC_VCNT 0xf 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* memory type definitions. */ 34*4882a593Smuzhiyun enum drm_rockchip_gem_mem_type { 35*4882a593Smuzhiyun /* Physically Continuous memory. */ 36*4882a593Smuzhiyun ROCKCHIP_BO_CONTIG = 1 << 0, 37*4882a593Smuzhiyun /* cachable mapping. */ 38*4882a593Smuzhiyun ROCKCHIP_BO_CACHABLE = 1 << 1, 39*4882a593Smuzhiyun /* write-combine mapping. */ 40*4882a593Smuzhiyun ROCKCHIP_BO_WC = 1 << 2, 41*4882a593Smuzhiyun ROCKCHIP_BO_SECURE = 1 << 3, 42*4882a593Smuzhiyun /* keep kmap for cma buffer or alloc kmap for other type memory */ 43*4882a593Smuzhiyun ROCKCHIP_BO_ALLOC_KMAP = 1 << 4, 44*4882a593Smuzhiyun /* alloc page with gfp_dma32 */ 45*4882a593Smuzhiyun ROCKCHIP_BO_DMA32 = 1 << 5, 46*4882a593Smuzhiyun ROCKCHIP_BO_MASK = ROCKCHIP_BO_CONTIG | ROCKCHIP_BO_CACHABLE | 47*4882a593Smuzhiyun ROCKCHIP_BO_WC | ROCKCHIP_BO_SECURE | ROCKCHIP_BO_ALLOC_KMAP | 48*4882a593Smuzhiyun ROCKCHIP_BO_DMA32, 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /** 52*4882a593Smuzhiyun * User-desired buffer creation information structure. 53*4882a593Smuzhiyun * 54*4882a593Smuzhiyun * @size: user-desired memory allocation size. 55*4882a593Smuzhiyun * @flags: user request for setting memory type or cache attributes. 56*4882a593Smuzhiyun * @handle: returned a handle to created gem object. 57*4882a593Smuzhiyun * - this handle will be set by gem module of kernel side. 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun struct drm_rockchip_gem_create { 60*4882a593Smuzhiyun uint64_t size; 61*4882a593Smuzhiyun uint32_t flags; 62*4882a593Smuzhiyun uint32_t handle; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct drm_rockchip_gem_phys { 66*4882a593Smuzhiyun uint32_t handle; 67*4882a593Smuzhiyun uint32_t phy_addr; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /** 71*4882a593Smuzhiyun * A structure for getting buffer offset. 72*4882a593Smuzhiyun * 73*4882a593Smuzhiyun * @handle: a pointer to gem object created. 74*4882a593Smuzhiyun * @pad: just padding to be 64-bit aligned. 75*4882a593Smuzhiyun * @offset: relatived offset value of the memory region allocated. 76*4882a593Smuzhiyun * - this value should be set by user. 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun struct drm_rockchip_gem_map_off { 79*4882a593Smuzhiyun uint32_t handle; 80*4882a593Smuzhiyun uint32_t pad; 81*4882a593Smuzhiyun uint64_t offset; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* acquire type definitions. */ 85*4882a593Smuzhiyun enum drm_rockchip_gem_cpu_acquire_type { 86*4882a593Smuzhiyun DRM_ROCKCHIP_GEM_CPU_ACQUIRE_SHARED = 0x0, 87*4882a593Smuzhiyun DRM_ROCKCHIP_GEM_CPU_ACQUIRE_EXCLUSIVE = 0x1, 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun enum rockchip_crtc_feture { 91*4882a593Smuzhiyun ROCKCHIP_DRM_CRTC_FEATURE_ALPHA_SCALE, 92*4882a593Smuzhiyun ROCKCHIP_DRM_CRTC_FEATURE_HDR10, 93*4882a593Smuzhiyun ROCKCHIP_DRM_CRTC_FEATURE_NEXT_HDR, 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun enum rockchip_plane_feture { 97*4882a593Smuzhiyun ROCKCHIP_DRM_PLANE_FEATURE_SCALE, 98*4882a593Smuzhiyun ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, 99*4882a593Smuzhiyun ROCKCHIP_DRM_PLANE_FEATURE_HDR2SDR, 100*4882a593Smuzhiyun ROCKCHIP_DRM_PLANE_FEATURE_SDR2HDR, 101*4882a593Smuzhiyun ROCKCHIP_DRM_PLANE_FEATURE_AFBDC, 102*4882a593Smuzhiyun ROCKCHIP_DRM_PLANE_FEATURE_PDAF_POS, 103*4882a593Smuzhiyun ROCKCHIP_DRM_PLANE_FEATURE_MAX, 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun enum rockchip_cabc_mode { 107*4882a593Smuzhiyun ROCKCHIP_DRM_CABC_MODE_DISABLE, 108*4882a593Smuzhiyun ROCKCHIP_DRM_CABC_MODE_NORMAL, 109*4882a593Smuzhiyun ROCKCHIP_DRM_CABC_MODE_LOWPOWER, 110*4882a593Smuzhiyun ROCKCHIP_DRM_CABC_MODE_USERSPACE, 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define DRM_ROCKCHIP_GEM_CREATE 0x00 114*4882a593Smuzhiyun #define DRM_ROCKCHIP_GEM_MAP_OFFSET 0x01 115*4882a593Smuzhiyun #define DRM_ROCKCHIP_GEM_CPU_ACQUIRE 0x02 116*4882a593Smuzhiyun #define DRM_ROCKCHIP_GEM_CPU_RELEASE 0x03 117*4882a593Smuzhiyun #define DRM_ROCKCHIP_GEM_GET_PHYS 0x04 118*4882a593Smuzhiyun #define DRM_ROCKCHIP_GET_VCNT_EVENT 0x05 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define DRM_IOCTL_ROCKCHIP_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ 121*4882a593Smuzhiyun DRM_ROCKCHIP_GEM_CREATE, struct drm_rockchip_gem_create) 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define DRM_IOCTL_ROCKCHIP_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + \ 124*4882a593Smuzhiyun DRM_ROCKCHIP_GEM_MAP_OFFSET, struct drm_rockchip_gem_map_off) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define DRM_IOCTL_ROCKCHIP_GEM_CPU_ACQUIRE DRM_IOWR(DRM_COMMAND_BASE + \ 127*4882a593Smuzhiyun DRM_ROCKCHIP_GEM_CPU_ACQUIRE, struct drm_rockchip_gem_cpu_acquire) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define DRM_IOCTL_ROCKCHIP_GEM_CPU_RELEASE DRM_IOWR(DRM_COMMAND_BASE + \ 130*4882a593Smuzhiyun DRM_ROCKCHIP_GEM_CPU_RELEASE, struct drm_rockchip_gem_cpu_release) 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define DRM_IOCTL_ROCKCHIP_GEM_GET_PHYS DRM_IOWR(DRM_COMMAND_BASE + \ 133*4882a593Smuzhiyun DRM_ROCKCHIP_GEM_GET_PHYS, struct drm_rockchip_gem_phys) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define DRM_IOCTL_ROCKCHIP_GET_VCNT_EVENT DRM_IOWR(DRM_COMMAND_BASE + \ 136*4882a593Smuzhiyun DRM_ROCKCHIP_GET_VCNT_EVENT, union drm_wait_vblank) 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #endif /* _UAPI_ROCKCHIP_DRM_H */ 139