xref: /OK3568_Linux_fs/kernel/include/uapi/drm/r128_drm.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
2*4882a593Smuzhiyun  * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
3*4882a593Smuzhiyun  */
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
6*4882a593Smuzhiyun  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7*4882a593Smuzhiyun  * All rights reserved.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
10*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
11*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
12*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
14*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * The above copyright notice and this permission notice (including the next
17*4882a593Smuzhiyun  * paragraph) shall be included in all copies or substantial portions of the
18*4882a593Smuzhiyun  * Software.
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
23*4882a593Smuzhiyun  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26*4882a593Smuzhiyun  * DEALINGS IN THE SOFTWARE.
27*4882a593Smuzhiyun  *
28*4882a593Smuzhiyun  * Authors:
29*4882a593Smuzhiyun  *    Gareth Hughes <gareth@valinux.com>
30*4882a593Smuzhiyun  *    Kevin E. Martin <martin@valinux.com>
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #ifndef __R128_DRM_H__
34*4882a593Smuzhiyun #define __R128_DRM_H__
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #include "drm.h"
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #if defined(__cplusplus)
39*4882a593Smuzhiyun extern "C" {
40*4882a593Smuzhiyun #endif
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* WARNING: If you change any of these defines, make sure to change the
43*4882a593Smuzhiyun  * defines in the X server file (r128_sarea.h)
44*4882a593Smuzhiyun  */
45*4882a593Smuzhiyun #ifndef __R128_SAREA_DEFINES__
46*4882a593Smuzhiyun #define __R128_SAREA_DEFINES__
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun /* What needs to be changed for the current vertex buffer?
49*4882a593Smuzhiyun  */
50*4882a593Smuzhiyun #define R128_UPLOAD_CONTEXT		0x001
51*4882a593Smuzhiyun #define R128_UPLOAD_SETUP		0x002
52*4882a593Smuzhiyun #define R128_UPLOAD_TEX0		0x004
53*4882a593Smuzhiyun #define R128_UPLOAD_TEX1		0x008
54*4882a593Smuzhiyun #define R128_UPLOAD_TEX0IMAGES		0x010
55*4882a593Smuzhiyun #define R128_UPLOAD_TEX1IMAGES		0x020
56*4882a593Smuzhiyun #define R128_UPLOAD_CORE		0x040
57*4882a593Smuzhiyun #define R128_UPLOAD_MASKS		0x080
58*4882a593Smuzhiyun #define R128_UPLOAD_WINDOW		0x100
59*4882a593Smuzhiyun #define R128_UPLOAD_CLIPRECTS		0x200	/* handled client-side */
60*4882a593Smuzhiyun #define R128_REQUIRE_QUIESCENCE		0x400
61*4882a593Smuzhiyun #define R128_UPLOAD_ALL			0x7ff
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun #define R128_FRONT			0x1
64*4882a593Smuzhiyun #define R128_BACK			0x2
65*4882a593Smuzhiyun #define R128_DEPTH			0x4
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /* Primitive types
68*4882a593Smuzhiyun  */
69*4882a593Smuzhiyun #define R128_POINTS			0x1
70*4882a593Smuzhiyun #define R128_LINES			0x2
71*4882a593Smuzhiyun #define R128_LINE_STRIP			0x3
72*4882a593Smuzhiyun #define R128_TRIANGLES			0x4
73*4882a593Smuzhiyun #define R128_TRIANGLE_FAN		0x5
74*4882a593Smuzhiyun #define R128_TRIANGLE_STRIP		0x6
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* Vertex/indirect buffer size
77*4882a593Smuzhiyun  */
78*4882a593Smuzhiyun #define R128_BUFFER_SIZE		16384
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* Byte offsets for indirect buffer data
81*4882a593Smuzhiyun  */
82*4882a593Smuzhiyun #define R128_INDEX_PRIM_OFFSET		20
83*4882a593Smuzhiyun #define R128_HOSTDATA_BLIT_OFFSET	32
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun /* Keep these small for testing.
86*4882a593Smuzhiyun  */
87*4882a593Smuzhiyun #define R128_NR_SAREA_CLIPRECTS		12
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun /* There are 2 heaps (local/AGP).  Each region within a heap is a
90*4882a593Smuzhiyun  *  minimum of 64k, and there are at most 64 of them per heap.
91*4882a593Smuzhiyun  */
92*4882a593Smuzhiyun #define R128_LOCAL_TEX_HEAP		0
93*4882a593Smuzhiyun #define R128_AGP_TEX_HEAP		1
94*4882a593Smuzhiyun #define R128_NR_TEX_HEAPS		2
95*4882a593Smuzhiyun #define R128_NR_TEX_REGIONS		64
96*4882a593Smuzhiyun #define R128_LOG_TEX_GRANULARITY	16
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define R128_NR_CONTEXT_REGS		12
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun #define R128_MAX_TEXTURE_LEVELS		11
101*4882a593Smuzhiyun #define R128_MAX_TEXTURE_UNITS		2
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun #endif				/* __R128_SAREA_DEFINES__ */
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun typedef struct {
106*4882a593Smuzhiyun 	/* Context state - can be written in one large chunk */
107*4882a593Smuzhiyun 	unsigned int dst_pitch_offset_c;
108*4882a593Smuzhiyun 	unsigned int dp_gui_master_cntl_c;
109*4882a593Smuzhiyun 	unsigned int sc_top_left_c;
110*4882a593Smuzhiyun 	unsigned int sc_bottom_right_c;
111*4882a593Smuzhiyun 	unsigned int z_offset_c;
112*4882a593Smuzhiyun 	unsigned int z_pitch_c;
113*4882a593Smuzhiyun 	unsigned int z_sten_cntl_c;
114*4882a593Smuzhiyun 	unsigned int tex_cntl_c;
115*4882a593Smuzhiyun 	unsigned int misc_3d_state_cntl_reg;
116*4882a593Smuzhiyun 	unsigned int texture_clr_cmp_clr_c;
117*4882a593Smuzhiyun 	unsigned int texture_clr_cmp_msk_c;
118*4882a593Smuzhiyun 	unsigned int fog_color_c;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	/* Texture state */
121*4882a593Smuzhiyun 	unsigned int tex_size_pitch_c;
122*4882a593Smuzhiyun 	unsigned int constant_color_c;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	/* Setup state */
125*4882a593Smuzhiyun 	unsigned int pm4_vc_fpu_setup;
126*4882a593Smuzhiyun 	unsigned int setup_cntl;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	/* Mask state */
129*4882a593Smuzhiyun 	unsigned int dp_write_mask;
130*4882a593Smuzhiyun 	unsigned int sten_ref_mask_c;
131*4882a593Smuzhiyun 	unsigned int plane_3d_mask_c;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	/* Window state */
134*4882a593Smuzhiyun 	unsigned int window_xy_offset;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	/* Core state */
137*4882a593Smuzhiyun 	unsigned int scale_3d_cntl;
138*4882a593Smuzhiyun } drm_r128_context_regs_t;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun /* Setup registers for each texture unit
141*4882a593Smuzhiyun  */
142*4882a593Smuzhiyun typedef struct {
143*4882a593Smuzhiyun 	unsigned int tex_cntl;
144*4882a593Smuzhiyun 	unsigned int tex_combine_cntl;
145*4882a593Smuzhiyun 	unsigned int tex_size_pitch;
146*4882a593Smuzhiyun 	unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
147*4882a593Smuzhiyun 	unsigned int tex_border_color;
148*4882a593Smuzhiyun } drm_r128_texture_regs_t;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun typedef struct drm_r128_sarea {
151*4882a593Smuzhiyun 	/* The channel for communication of state information to the kernel
152*4882a593Smuzhiyun 	 * on firing a vertex buffer.
153*4882a593Smuzhiyun 	 */
154*4882a593Smuzhiyun 	drm_r128_context_regs_t context_state;
155*4882a593Smuzhiyun 	drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
156*4882a593Smuzhiyun 	unsigned int dirty;
157*4882a593Smuzhiyun 	unsigned int vertsize;
158*4882a593Smuzhiyun 	unsigned int vc_format;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	/* The current cliprects, or a subset thereof.
161*4882a593Smuzhiyun 	 */
162*4882a593Smuzhiyun 	struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
163*4882a593Smuzhiyun 	unsigned int nbox;
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	/* Counters for client-side throttling of rendering clients.
166*4882a593Smuzhiyun 	 */
167*4882a593Smuzhiyun 	unsigned int last_frame;
168*4882a593Smuzhiyun 	unsigned int last_dispatch;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
171*4882a593Smuzhiyun 	unsigned int tex_age[R128_NR_TEX_HEAPS];
172*4882a593Smuzhiyun 	int ctx_owner;
173*4882a593Smuzhiyun 	int pfAllowPageFlip;	/* number of 3d windows (0,1,2 or more) */
174*4882a593Smuzhiyun 	int pfCurrentPage;	/* which buffer is being displayed? */
175*4882a593Smuzhiyun } drm_r128_sarea_t;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun /* WARNING: If you change any of these defines, make sure to change the
178*4882a593Smuzhiyun  * defines in the Xserver file (xf86drmR128.h)
179*4882a593Smuzhiyun  */
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun /* Rage 128 specific ioctls
182*4882a593Smuzhiyun  * The device specific ioctl range is 0x40 to 0x79.
183*4882a593Smuzhiyun  */
184*4882a593Smuzhiyun #define DRM_R128_INIT       0x00
185*4882a593Smuzhiyun #define DRM_R128_CCE_START  0x01
186*4882a593Smuzhiyun #define DRM_R128_CCE_STOP   0x02
187*4882a593Smuzhiyun #define DRM_R128_CCE_RESET  0x03
188*4882a593Smuzhiyun #define DRM_R128_CCE_IDLE   0x04
189*4882a593Smuzhiyun /* 0x05 not used */
190*4882a593Smuzhiyun #define DRM_R128_RESET      0x06
191*4882a593Smuzhiyun #define DRM_R128_SWAP       0x07
192*4882a593Smuzhiyun #define DRM_R128_CLEAR      0x08
193*4882a593Smuzhiyun #define DRM_R128_VERTEX     0x09
194*4882a593Smuzhiyun #define DRM_R128_INDICES    0x0a
195*4882a593Smuzhiyun #define DRM_R128_BLIT       0x0b
196*4882a593Smuzhiyun #define DRM_R128_DEPTH      0x0c
197*4882a593Smuzhiyun #define DRM_R128_STIPPLE    0x0d
198*4882a593Smuzhiyun /* 0x0e not used */
199*4882a593Smuzhiyun #define DRM_R128_INDIRECT   0x0f
200*4882a593Smuzhiyun #define DRM_R128_FULLSCREEN 0x10
201*4882a593Smuzhiyun #define DRM_R128_CLEAR2     0x11
202*4882a593Smuzhiyun #define DRM_R128_GETPARAM   0x12
203*4882a593Smuzhiyun #define DRM_R128_FLIP       0x13
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun #define DRM_IOCTL_R128_INIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
206*4882a593Smuzhiyun #define DRM_IOCTL_R128_CCE_START  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_START)
207*4882a593Smuzhiyun #define DRM_IOCTL_R128_CCE_STOP   DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
208*4882a593Smuzhiyun #define DRM_IOCTL_R128_CCE_RESET  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
209*4882a593Smuzhiyun #define DRM_IOCTL_R128_CCE_IDLE   DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
210*4882a593Smuzhiyun /* 0x05 not used */
211*4882a593Smuzhiyun #define DRM_IOCTL_R128_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_R128_RESET)
212*4882a593Smuzhiyun #define DRM_IOCTL_R128_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_SWAP)
213*4882a593Smuzhiyun #define DRM_IOCTL_R128_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
214*4882a593Smuzhiyun #define DRM_IOCTL_R128_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
215*4882a593Smuzhiyun #define DRM_IOCTL_R128_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
216*4882a593Smuzhiyun #define DRM_IOCTL_R128_BLIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
217*4882a593Smuzhiyun #define DRM_IOCTL_R128_DEPTH      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
218*4882a593Smuzhiyun #define DRM_IOCTL_R128_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
219*4882a593Smuzhiyun /* 0x0e not used */
220*4882a593Smuzhiyun #define DRM_IOCTL_R128_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
221*4882a593Smuzhiyun #define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
222*4882a593Smuzhiyun #define DRM_IOCTL_R128_CLEAR2     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
223*4882a593Smuzhiyun #define DRM_IOCTL_R128_GETPARAM   DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
224*4882a593Smuzhiyun #define DRM_IOCTL_R128_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_FLIP)
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun typedef struct drm_r128_init {
227*4882a593Smuzhiyun 	enum {
228*4882a593Smuzhiyun 		R128_INIT_CCE = 0x01,
229*4882a593Smuzhiyun 		R128_CLEANUP_CCE = 0x02
230*4882a593Smuzhiyun 	} func;
231*4882a593Smuzhiyun 	unsigned long sarea_priv_offset;
232*4882a593Smuzhiyun 	int is_pci;
233*4882a593Smuzhiyun 	int cce_mode;
234*4882a593Smuzhiyun 	int cce_secure;
235*4882a593Smuzhiyun 	int ring_size;
236*4882a593Smuzhiyun 	int usec_timeout;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	unsigned int fb_bpp;
239*4882a593Smuzhiyun 	unsigned int front_offset, front_pitch;
240*4882a593Smuzhiyun 	unsigned int back_offset, back_pitch;
241*4882a593Smuzhiyun 	unsigned int depth_bpp;
242*4882a593Smuzhiyun 	unsigned int depth_offset, depth_pitch;
243*4882a593Smuzhiyun 	unsigned int span_offset;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	unsigned long fb_offset;
246*4882a593Smuzhiyun 	unsigned long mmio_offset;
247*4882a593Smuzhiyun 	unsigned long ring_offset;
248*4882a593Smuzhiyun 	unsigned long ring_rptr_offset;
249*4882a593Smuzhiyun 	unsigned long buffers_offset;
250*4882a593Smuzhiyun 	unsigned long agp_textures_offset;
251*4882a593Smuzhiyun } drm_r128_init_t;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun typedef struct drm_r128_cce_stop {
254*4882a593Smuzhiyun 	int flush;
255*4882a593Smuzhiyun 	int idle;
256*4882a593Smuzhiyun } drm_r128_cce_stop_t;
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun typedef struct drm_r128_clear {
259*4882a593Smuzhiyun 	unsigned int flags;
260*4882a593Smuzhiyun 	unsigned int clear_color;
261*4882a593Smuzhiyun 	unsigned int clear_depth;
262*4882a593Smuzhiyun 	unsigned int color_mask;
263*4882a593Smuzhiyun 	unsigned int depth_mask;
264*4882a593Smuzhiyun } drm_r128_clear_t;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun typedef struct drm_r128_vertex {
267*4882a593Smuzhiyun 	int prim;
268*4882a593Smuzhiyun 	int idx;		/* Index of vertex buffer */
269*4882a593Smuzhiyun 	int count;		/* Number of vertices in buffer */
270*4882a593Smuzhiyun 	int discard;		/* Client finished with buffer? */
271*4882a593Smuzhiyun } drm_r128_vertex_t;
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun typedef struct drm_r128_indices {
274*4882a593Smuzhiyun 	int prim;
275*4882a593Smuzhiyun 	int idx;
276*4882a593Smuzhiyun 	int start;
277*4882a593Smuzhiyun 	int end;
278*4882a593Smuzhiyun 	int discard;		/* Client finished with buffer? */
279*4882a593Smuzhiyun } drm_r128_indices_t;
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun typedef struct drm_r128_blit {
282*4882a593Smuzhiyun 	int idx;
283*4882a593Smuzhiyun 	int pitch;
284*4882a593Smuzhiyun 	int offset;
285*4882a593Smuzhiyun 	int format;
286*4882a593Smuzhiyun 	unsigned short x, y;
287*4882a593Smuzhiyun 	unsigned short width, height;
288*4882a593Smuzhiyun } drm_r128_blit_t;
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun typedef struct drm_r128_depth {
291*4882a593Smuzhiyun 	enum {
292*4882a593Smuzhiyun 		R128_WRITE_SPAN = 0x01,
293*4882a593Smuzhiyun 		R128_WRITE_PIXELS = 0x02,
294*4882a593Smuzhiyun 		R128_READ_SPAN = 0x03,
295*4882a593Smuzhiyun 		R128_READ_PIXELS = 0x04
296*4882a593Smuzhiyun 	} func;
297*4882a593Smuzhiyun 	int n;
298*4882a593Smuzhiyun 	int __user *x;
299*4882a593Smuzhiyun 	int __user *y;
300*4882a593Smuzhiyun 	unsigned int __user *buffer;
301*4882a593Smuzhiyun 	unsigned char __user *mask;
302*4882a593Smuzhiyun } drm_r128_depth_t;
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun typedef struct drm_r128_stipple {
305*4882a593Smuzhiyun 	unsigned int __user *mask;
306*4882a593Smuzhiyun } drm_r128_stipple_t;
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun typedef struct drm_r128_indirect {
309*4882a593Smuzhiyun 	int idx;
310*4882a593Smuzhiyun 	int start;
311*4882a593Smuzhiyun 	int end;
312*4882a593Smuzhiyun 	int discard;
313*4882a593Smuzhiyun } drm_r128_indirect_t;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun typedef struct drm_r128_fullscreen {
316*4882a593Smuzhiyun 	enum {
317*4882a593Smuzhiyun 		R128_INIT_FULLSCREEN = 0x01,
318*4882a593Smuzhiyun 		R128_CLEANUP_FULLSCREEN = 0x02
319*4882a593Smuzhiyun 	} func;
320*4882a593Smuzhiyun } drm_r128_fullscreen_t;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun /* 2.3: An ioctl to get parameters that aren't available to the 3d
323*4882a593Smuzhiyun  * client any other way.
324*4882a593Smuzhiyun  */
325*4882a593Smuzhiyun #define R128_PARAM_IRQ_NR            1
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun typedef struct drm_r128_getparam {
328*4882a593Smuzhiyun 	int param;
329*4882a593Smuzhiyun 	void __user *value;
330*4882a593Smuzhiyun } drm_r128_getparam_t;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun #if defined(__cplusplus)
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun #endif
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun #endif
337