1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright © 2014-2018 Broadcom 4*4882a593Smuzhiyun * Copyright © 2019 Collabora ltd. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef _PANFROST_DRM_H_ 7*4882a593Smuzhiyun #define _PANFROST_DRM_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "drm.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #if defined(__cplusplus) 12*4882a593Smuzhiyun extern "C" { 13*4882a593Smuzhiyun #endif 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define DRM_PANFROST_SUBMIT 0x00 16*4882a593Smuzhiyun #define DRM_PANFROST_WAIT_BO 0x01 17*4882a593Smuzhiyun #define DRM_PANFROST_CREATE_BO 0x02 18*4882a593Smuzhiyun #define DRM_PANFROST_MMAP_BO 0x03 19*4882a593Smuzhiyun #define DRM_PANFROST_GET_PARAM 0x04 20*4882a593Smuzhiyun #define DRM_PANFROST_GET_BO_OFFSET 0x05 21*4882a593Smuzhiyun #define DRM_PANFROST_PERFCNT_ENABLE 0x06 22*4882a593Smuzhiyun #define DRM_PANFROST_PERFCNT_DUMP 0x07 23*4882a593Smuzhiyun #define DRM_PANFROST_MADVISE 0x08 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define DRM_IOCTL_PANFROST_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_SUBMIT, struct drm_panfrost_submit) 26*4882a593Smuzhiyun #define DRM_IOCTL_PANFROST_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_WAIT_BO, struct drm_panfrost_wait_bo) 27*4882a593Smuzhiyun #define DRM_IOCTL_PANFROST_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_CREATE_BO, struct drm_panfrost_create_bo) 28*4882a593Smuzhiyun #define DRM_IOCTL_PANFROST_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MMAP_BO, struct drm_panfrost_mmap_bo) 29*4882a593Smuzhiyun #define DRM_IOCTL_PANFROST_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_PARAM, struct drm_panfrost_get_param) 30*4882a593Smuzhiyun #define DRM_IOCTL_PANFROST_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_GET_BO_OFFSET, struct drm_panfrost_get_bo_offset) 31*4882a593Smuzhiyun #define DRM_IOCTL_PANFROST_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_PANFROST_MADVISE, struct drm_panfrost_madvise) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * Unstable ioctl(s): only exposed when the unsafe unstable_ioctls module 35*4882a593Smuzhiyun * param is set to true. 36*4882a593Smuzhiyun * All these ioctl(s) are subject to deprecation, so please don't rely on 37*4882a593Smuzhiyun * them for anything but debugging purpose. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun #define DRM_IOCTL_PANFROST_PERFCNT_ENABLE DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_ENABLE, struct drm_panfrost_perfcnt_enable) 40*4882a593Smuzhiyun #define DRM_IOCTL_PANFROST_PERFCNT_DUMP DRM_IOW(DRM_COMMAND_BASE + DRM_PANFROST_PERFCNT_DUMP, struct drm_panfrost_perfcnt_dump) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define PANFROST_JD_REQ_FS (1 << 0) 43*4882a593Smuzhiyun /** 44*4882a593Smuzhiyun * struct drm_panfrost_submit - ioctl argument for submitting commands to the 3D 45*4882a593Smuzhiyun * engine. 46*4882a593Smuzhiyun * 47*4882a593Smuzhiyun * This asks the kernel to have the GPU execute a render command list. 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun struct drm_panfrost_submit { 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /** Address to GPU mapping of job descriptor */ 52*4882a593Smuzhiyun __u64 jc; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /** An optional array of sync objects to wait on before starting this job. */ 55*4882a593Smuzhiyun __u64 in_syncs; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /** Number of sync objects to wait on before starting this job. */ 58*4882a593Smuzhiyun __u32 in_sync_count; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /** An optional sync object to place the completion fence in. */ 61*4882a593Smuzhiyun __u32 out_sync; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /** Pointer to a u32 array of the BOs that are referenced by the job. */ 64*4882a593Smuzhiyun __u64 bo_handles; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /** Number of BO handles passed in (size is that times 4). */ 67*4882a593Smuzhiyun __u32 bo_handle_count; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /** A combination of PANFROST_JD_REQ_* */ 70*4882a593Smuzhiyun __u32 requirements; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /** 74*4882a593Smuzhiyun * struct drm_panfrost_wait_bo - ioctl argument for waiting for 75*4882a593Smuzhiyun * completion of the last DRM_PANFROST_SUBMIT on a BO. 76*4882a593Smuzhiyun * 77*4882a593Smuzhiyun * This is useful for cases where multiple processes might be 78*4882a593Smuzhiyun * rendering to a BO and you want to wait for all rendering to be 79*4882a593Smuzhiyun * completed. 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun struct drm_panfrost_wait_bo { 82*4882a593Smuzhiyun __u32 handle; 83*4882a593Smuzhiyun __u32 pad; 84*4882a593Smuzhiyun __s64 timeout_ns; /* absolute */ 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define PANFROST_BO_NOEXEC 1 88*4882a593Smuzhiyun #define PANFROST_BO_HEAP 2 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /** 91*4882a593Smuzhiyun * struct drm_panfrost_create_bo - ioctl argument for creating Panfrost BOs. 92*4882a593Smuzhiyun * 93*4882a593Smuzhiyun * There are currently no values for the flags argument, but it may be 94*4882a593Smuzhiyun * used in a future extension. 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun struct drm_panfrost_create_bo { 97*4882a593Smuzhiyun __u32 size; 98*4882a593Smuzhiyun __u32 flags; 99*4882a593Smuzhiyun /** Returned GEM handle for the BO. */ 100*4882a593Smuzhiyun __u32 handle; 101*4882a593Smuzhiyun /* Pad, must be zero-filled. */ 102*4882a593Smuzhiyun __u32 pad; 103*4882a593Smuzhiyun /** 104*4882a593Smuzhiyun * Returned offset for the BO in the GPU address space. This offset 105*4882a593Smuzhiyun * is private to the DRM fd and is valid for the lifetime of the GEM 106*4882a593Smuzhiyun * handle. 107*4882a593Smuzhiyun * 108*4882a593Smuzhiyun * This offset value will always be nonzero, since various HW 109*4882a593Smuzhiyun * units treat 0 specially. 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun __u64 offset; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /** 115*4882a593Smuzhiyun * struct drm_panfrost_mmap_bo - ioctl argument for mapping Panfrost BOs. 116*4882a593Smuzhiyun * 117*4882a593Smuzhiyun * This doesn't actually perform an mmap. Instead, it returns the 118*4882a593Smuzhiyun * offset you need to use in an mmap on the DRM device node. This 119*4882a593Smuzhiyun * means that tools like valgrind end up knowing about the mapped 120*4882a593Smuzhiyun * memory. 121*4882a593Smuzhiyun * 122*4882a593Smuzhiyun * There are currently no values for the flags argument, but it may be 123*4882a593Smuzhiyun * used in a future extension. 124*4882a593Smuzhiyun */ 125*4882a593Smuzhiyun struct drm_panfrost_mmap_bo { 126*4882a593Smuzhiyun /** Handle for the object being mapped. */ 127*4882a593Smuzhiyun __u32 handle; 128*4882a593Smuzhiyun __u32 flags; 129*4882a593Smuzhiyun /** offset into the drm node to use for subsequent mmap call. */ 130*4882a593Smuzhiyun __u64 offset; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun enum drm_panfrost_param { 134*4882a593Smuzhiyun DRM_PANFROST_PARAM_GPU_PROD_ID, 135*4882a593Smuzhiyun DRM_PANFROST_PARAM_GPU_REVISION, 136*4882a593Smuzhiyun DRM_PANFROST_PARAM_SHADER_PRESENT, 137*4882a593Smuzhiyun DRM_PANFROST_PARAM_TILER_PRESENT, 138*4882a593Smuzhiyun DRM_PANFROST_PARAM_L2_PRESENT, 139*4882a593Smuzhiyun DRM_PANFROST_PARAM_STACK_PRESENT, 140*4882a593Smuzhiyun DRM_PANFROST_PARAM_AS_PRESENT, 141*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_PRESENT, 142*4882a593Smuzhiyun DRM_PANFROST_PARAM_L2_FEATURES, 143*4882a593Smuzhiyun DRM_PANFROST_PARAM_CORE_FEATURES, 144*4882a593Smuzhiyun DRM_PANFROST_PARAM_TILER_FEATURES, 145*4882a593Smuzhiyun DRM_PANFROST_PARAM_MEM_FEATURES, 146*4882a593Smuzhiyun DRM_PANFROST_PARAM_MMU_FEATURES, 147*4882a593Smuzhiyun DRM_PANFROST_PARAM_THREAD_FEATURES, 148*4882a593Smuzhiyun DRM_PANFROST_PARAM_MAX_THREADS, 149*4882a593Smuzhiyun DRM_PANFROST_PARAM_THREAD_MAX_WORKGROUP_SZ, 150*4882a593Smuzhiyun DRM_PANFROST_PARAM_THREAD_MAX_BARRIER_SZ, 151*4882a593Smuzhiyun DRM_PANFROST_PARAM_COHERENCY_FEATURES, 152*4882a593Smuzhiyun DRM_PANFROST_PARAM_TEXTURE_FEATURES0, 153*4882a593Smuzhiyun DRM_PANFROST_PARAM_TEXTURE_FEATURES1, 154*4882a593Smuzhiyun DRM_PANFROST_PARAM_TEXTURE_FEATURES2, 155*4882a593Smuzhiyun DRM_PANFROST_PARAM_TEXTURE_FEATURES3, 156*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES0, 157*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES1, 158*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES2, 159*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES3, 160*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES4, 161*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES5, 162*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES6, 163*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES7, 164*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES8, 165*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES9, 166*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES10, 167*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES11, 168*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES12, 169*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES13, 170*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES14, 171*4882a593Smuzhiyun DRM_PANFROST_PARAM_JS_FEATURES15, 172*4882a593Smuzhiyun DRM_PANFROST_PARAM_NR_CORE_GROUPS, 173*4882a593Smuzhiyun DRM_PANFROST_PARAM_THREAD_TLS_ALLOC, 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun struct drm_panfrost_get_param { 177*4882a593Smuzhiyun __u32 param; 178*4882a593Smuzhiyun __u32 pad; 179*4882a593Smuzhiyun __u64 value; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /** 183*4882a593Smuzhiyun * Returns the offset for the BO in the GPU address space for this DRM fd. 184*4882a593Smuzhiyun * This is the same value returned by drm_panfrost_create_bo, if that was called 185*4882a593Smuzhiyun * from this DRM fd. 186*4882a593Smuzhiyun */ 187*4882a593Smuzhiyun struct drm_panfrost_get_bo_offset { 188*4882a593Smuzhiyun __u32 handle; 189*4882a593Smuzhiyun __u32 pad; 190*4882a593Smuzhiyun __u64 offset; 191*4882a593Smuzhiyun }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun struct drm_panfrost_perfcnt_enable { 194*4882a593Smuzhiyun __u32 enable; 195*4882a593Smuzhiyun /* 196*4882a593Smuzhiyun * On bifrost we have 2 sets of counters, this parameter defines the 197*4882a593Smuzhiyun * one to track. 198*4882a593Smuzhiyun */ 199*4882a593Smuzhiyun __u32 counterset; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun struct drm_panfrost_perfcnt_dump { 203*4882a593Smuzhiyun __u64 buf_ptr; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun /* madvise provides a way to tell the kernel in case a buffers contents 207*4882a593Smuzhiyun * can be discarded under memory pressure, which is useful for userspace 208*4882a593Smuzhiyun * bo cache where we want to optimistically hold on to buffer allocate 209*4882a593Smuzhiyun * and potential mmap, but allow the pages to be discarded under memory 210*4882a593Smuzhiyun * pressure. 211*4882a593Smuzhiyun * 212*4882a593Smuzhiyun * Typical usage would involve madvise(DONTNEED) when buffer enters BO 213*4882a593Smuzhiyun * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache. 214*4882a593Smuzhiyun * In the WILLNEED case, 'retained' indicates to userspace whether the 215*4882a593Smuzhiyun * backing pages still exist. 216*4882a593Smuzhiyun */ 217*4882a593Smuzhiyun #define PANFROST_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */ 218*4882a593Smuzhiyun #define PANFROST_MADV_DONTNEED 1 /* backing pages not needed */ 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun struct drm_panfrost_madvise { 221*4882a593Smuzhiyun __u32 handle; /* in, GEM handle */ 222*4882a593Smuzhiyun __u32 madv; /* in, PANFROST_MADV_x */ 223*4882a593Smuzhiyun __u32 retained; /* out, whether backing store still exists */ 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #if defined(__cplusplus) 227*4882a593Smuzhiyun } 228*4882a593Smuzhiyun #endif 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun #endif /* _PANFROST_DRM_H_ */ 231