1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun #ifndef __SOUND_WSS_H 3*4882a593Smuzhiyun #define __SOUND_WSS_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 7*4882a593Smuzhiyun * Definitions for CS4231 & InterWave chips & compatible chips 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <sound/control.h> 11*4882a593Smuzhiyun #include <sound/pcm.h> 12*4882a593Smuzhiyun #include <sound/timer.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <sound/cs4231-regs.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* defines for codec.mode */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define WSS_MODE_NONE 0x0000 19*4882a593Smuzhiyun #define WSS_MODE_PLAY 0x0001 20*4882a593Smuzhiyun #define WSS_MODE_RECORD 0x0002 21*4882a593Smuzhiyun #define WSS_MODE_TIMER 0x0004 22*4882a593Smuzhiyun #define WSS_MODE_OPEN (WSS_MODE_PLAY|WSS_MODE_RECORD|WSS_MODE_TIMER) 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* defines for codec.hardware */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define WSS_HW_DETECT 0x0000 /* let CS4231 driver detect chip */ 27*4882a593Smuzhiyun #define WSS_HW_DETECT3 0x0001 /* allow mode 3 */ 28*4882a593Smuzhiyun #define WSS_HW_TYPE_MASK 0xff00 /* type mask */ 29*4882a593Smuzhiyun #define WSS_HW_CS4231_MASK 0x0100 /* CS4231 serie */ 30*4882a593Smuzhiyun #define WSS_HW_CS4231 0x0100 /* CS4231 chip */ 31*4882a593Smuzhiyun #define WSS_HW_CS4231A 0x0101 /* CS4231A chip */ 32*4882a593Smuzhiyun #define WSS_HW_AD1845 0x0102 /* AD1845 chip */ 33*4882a593Smuzhiyun #define WSS_HW_CS4232_MASK 0x0200 /* CS4232 serie (has control ports) */ 34*4882a593Smuzhiyun #define WSS_HW_CS4232 0x0200 /* CS4232 */ 35*4882a593Smuzhiyun #define WSS_HW_CS4232A 0x0201 /* CS4232A */ 36*4882a593Smuzhiyun #define WSS_HW_CS4236 0x0202 /* CS4236 */ 37*4882a593Smuzhiyun #define WSS_HW_CS4236B_MASK 0x0400 /* CS4236B serie (has extended control regs) */ 38*4882a593Smuzhiyun #define WSS_HW_CS4235 0x0400 /* CS4235 - Crystal Clear (tm) stereo enhancement */ 39*4882a593Smuzhiyun #define WSS_HW_CS4236B 0x0401 /* CS4236B */ 40*4882a593Smuzhiyun #define WSS_HW_CS4237B 0x0402 /* CS4237B - SRS 3D */ 41*4882a593Smuzhiyun #define WSS_HW_CS4238B 0x0403 /* CS4238B - QSOUND 3D */ 42*4882a593Smuzhiyun #define WSS_HW_CS4239 0x0404 /* CS4239 - Crystal Clear (tm) stereo enhancement */ 43*4882a593Smuzhiyun #define WSS_HW_AD1848_MASK 0x0800 /* AD1848 serie (half duplex) */ 44*4882a593Smuzhiyun #define WSS_HW_AD1847 0x0801 /* AD1847 chip */ 45*4882a593Smuzhiyun #define WSS_HW_AD1848 0x0802 /* AD1848 chip */ 46*4882a593Smuzhiyun #define WSS_HW_CS4248 0x0803 /* CS4248 chip */ 47*4882a593Smuzhiyun #define WSS_HW_CMI8330 0x0804 /* CMI8330 chip */ 48*4882a593Smuzhiyun #define WSS_HW_THINKPAD 0x0805 /* Thinkpad 360/750/755 */ 49*4882a593Smuzhiyun /* compatible, but clones */ 50*4882a593Smuzhiyun #define WSS_HW_INTERWAVE 0x1000 /* InterWave chip */ 51*4882a593Smuzhiyun #define WSS_HW_OPL3SA2 0x1101 /* OPL3-SA2 chip, similar to cs4231 */ 52*4882a593Smuzhiyun #define WSS_HW_OPTI93X 0x1102 /* Opti 930/931/933 */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* defines for codec.hwshare */ 55*4882a593Smuzhiyun #define WSS_HWSHARE_IRQ (1<<0) 56*4882a593Smuzhiyun #define WSS_HWSHARE_DMA1 (1<<1) 57*4882a593Smuzhiyun #define WSS_HWSHARE_DMA2 (1<<2) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* IBM Thinkpad specific stuff */ 60*4882a593Smuzhiyun #define AD1848_THINKPAD_CTL_PORT1 0x15e8 61*4882a593Smuzhiyun #define AD1848_THINKPAD_CTL_PORT2 0x15e9 62*4882a593Smuzhiyun #define AD1848_THINKPAD_CS4248_ENABLE_BIT 0x02 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct snd_wss { 65*4882a593Smuzhiyun unsigned long port; /* base i/o port */ 66*4882a593Smuzhiyun struct resource *res_port; 67*4882a593Smuzhiyun unsigned long cport; /* control base i/o port (CS4236) */ 68*4882a593Smuzhiyun struct resource *res_cport; 69*4882a593Smuzhiyun int irq; /* IRQ line */ 70*4882a593Smuzhiyun int dma1; /* playback DMA */ 71*4882a593Smuzhiyun int dma2; /* record DMA */ 72*4882a593Smuzhiyun unsigned short version; /* version of CODEC chip */ 73*4882a593Smuzhiyun unsigned short mode; /* see to WSS_MODE_XXXX */ 74*4882a593Smuzhiyun unsigned short hardware; /* see to WSS_HW_XXXX */ 75*4882a593Smuzhiyun unsigned short hwshare; /* shared resources */ 76*4882a593Smuzhiyun unsigned short single_dma:1, /* forced single DMA mode (GUS 16-bit */ 77*4882a593Smuzhiyun /* daughter board) or dma1 == dma2 */ 78*4882a593Smuzhiyun ebus_flag:1, /* SPARC: EBUS present */ 79*4882a593Smuzhiyun thinkpad_flag:1; /* Thinkpad CS4248 needs extra help */ 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct snd_card *card; 82*4882a593Smuzhiyun struct snd_pcm *pcm; 83*4882a593Smuzhiyun struct snd_pcm_substream *playback_substream; 84*4882a593Smuzhiyun struct snd_pcm_substream *capture_substream; 85*4882a593Smuzhiyun struct snd_timer *timer; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun unsigned char image[32]; /* registers image */ 88*4882a593Smuzhiyun unsigned char eimage[32]; /* extended registers image */ 89*4882a593Smuzhiyun unsigned char cimage[16]; /* control registers image */ 90*4882a593Smuzhiyun int mce_bit; 91*4882a593Smuzhiyun int calibrate_mute; 92*4882a593Smuzhiyun int sw_3d_bit; 93*4882a593Smuzhiyun unsigned int p_dma_size; 94*4882a593Smuzhiyun unsigned int c_dma_size; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun spinlock_t reg_lock; 97*4882a593Smuzhiyun struct mutex mce_mutex; 98*4882a593Smuzhiyun struct mutex open_mutex; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun int (*rate_constraint) (struct snd_pcm_runtime *runtime); 101*4882a593Smuzhiyun void (*set_playback_format) (struct snd_wss *chip, 102*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params, 103*4882a593Smuzhiyun unsigned char pdfr); 104*4882a593Smuzhiyun void (*set_capture_format) (struct snd_wss *chip, 105*4882a593Smuzhiyun struct snd_pcm_hw_params *hw_params, 106*4882a593Smuzhiyun unsigned char cdfr); 107*4882a593Smuzhiyun void (*trigger) (struct snd_wss *chip, unsigned int what, int start); 108*4882a593Smuzhiyun #ifdef CONFIG_PM 109*4882a593Smuzhiyun void (*suspend) (struct snd_wss *chip); 110*4882a593Smuzhiyun void (*resume) (struct snd_wss *chip); 111*4882a593Smuzhiyun #endif 112*4882a593Smuzhiyun void *dma_private_data; 113*4882a593Smuzhiyun int (*claim_dma) (struct snd_wss *chip, 114*4882a593Smuzhiyun void *dma_private_data, int dma); 115*4882a593Smuzhiyun int (*release_dma) (struct snd_wss *chip, 116*4882a593Smuzhiyun void *dma_private_data, int dma); 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* exported functions */ 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char val); 122*4882a593Smuzhiyun unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg); 123*4882a593Smuzhiyun void snd_cs4236_ext_out(struct snd_wss *chip, 124*4882a593Smuzhiyun unsigned char reg, unsigned char val); 125*4882a593Smuzhiyun unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg); 126*4882a593Smuzhiyun void snd_wss_mce_up(struct snd_wss *chip); 127*4882a593Smuzhiyun void snd_wss_mce_down(struct snd_wss *chip); 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun void snd_wss_overrange(struct snd_wss *chip); 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun irqreturn_t snd_wss_interrupt(int irq, void *dev_id); 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun const char *snd_wss_chip_id(struct snd_wss *chip); 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun int snd_wss_create(struct snd_card *card, 136*4882a593Smuzhiyun unsigned long port, 137*4882a593Smuzhiyun unsigned long cport, 138*4882a593Smuzhiyun int irq, int dma1, int dma2, 139*4882a593Smuzhiyun unsigned short hardware, 140*4882a593Smuzhiyun unsigned short hwshare, 141*4882a593Smuzhiyun struct snd_wss **rchip); 142*4882a593Smuzhiyun int snd_wss_pcm(struct snd_wss *chip, int device); 143*4882a593Smuzhiyun int snd_wss_timer(struct snd_wss *chip, int device); 144*4882a593Smuzhiyun int snd_wss_mixer(struct snd_wss *chip); 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction); 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun int snd_cs4236_create(struct snd_card *card, 149*4882a593Smuzhiyun unsigned long port, 150*4882a593Smuzhiyun unsigned long cport, 151*4882a593Smuzhiyun int irq, int dma1, int dma2, 152*4882a593Smuzhiyun unsigned short hardware, 153*4882a593Smuzhiyun unsigned short hwshare, 154*4882a593Smuzhiyun struct snd_wss **rchip); 155*4882a593Smuzhiyun int snd_cs4236_pcm(struct snd_wss *chip, int device); 156*4882a593Smuzhiyun int snd_cs4236_mixer(struct snd_wss *chip); 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* 159*4882a593Smuzhiyun * mixer library 160*4882a593Smuzhiyun */ 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define WSS_SINGLE(xname, xindex, reg, shift, mask, invert) \ 163*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 164*4882a593Smuzhiyun .name = xname, \ 165*4882a593Smuzhiyun .index = xindex, \ 166*4882a593Smuzhiyun .info = snd_wss_info_single, \ 167*4882a593Smuzhiyun .get = snd_wss_get_single, \ 168*4882a593Smuzhiyun .put = snd_wss_put_single, \ 169*4882a593Smuzhiyun .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun int snd_wss_info_single(struct snd_kcontrol *kcontrol, 172*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo); 173*4882a593Smuzhiyun int snd_wss_get_single(struct snd_kcontrol *kcontrol, 174*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol); 175*4882a593Smuzhiyun int snd_wss_put_single(struct snd_kcontrol *kcontrol, 176*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol); 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun #define WSS_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ 179*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 180*4882a593Smuzhiyun .name = xname, \ 181*4882a593Smuzhiyun .index = xindex, \ 182*4882a593Smuzhiyun .info = snd_wss_info_double, \ 183*4882a593Smuzhiyun .get = snd_wss_get_double, \ 184*4882a593Smuzhiyun .put = snd_wss_put_double, \ 185*4882a593Smuzhiyun .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \ 186*4882a593Smuzhiyun (shift_right << 19) | (mask << 24) | (invert << 22) } 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun #define WSS_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ 189*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 190*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ 191*4882a593Smuzhiyun .name = xname, \ 192*4882a593Smuzhiyun .index = xindex, \ 193*4882a593Smuzhiyun .info = snd_wss_info_single, \ 194*4882a593Smuzhiyun .get = snd_wss_get_single, \ 195*4882a593Smuzhiyun .put = snd_wss_put_single, \ 196*4882a593Smuzhiyun .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ 197*4882a593Smuzhiyun .tlv = { .p = (xtlv) } } 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun #define WSS_DOUBLE_TLV(xname, xindex, left_reg, right_reg, \ 200*4882a593Smuzhiyun shift_left, shift_right, mask, invert, xtlv) \ 201*4882a593Smuzhiyun { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 202*4882a593Smuzhiyun .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ 203*4882a593Smuzhiyun .name = xname, \ 204*4882a593Smuzhiyun .index = xindex, \ 205*4882a593Smuzhiyun .info = snd_wss_info_double, \ 206*4882a593Smuzhiyun .get = snd_wss_get_double, \ 207*4882a593Smuzhiyun .put = snd_wss_put_double, \ 208*4882a593Smuzhiyun .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \ 209*4882a593Smuzhiyun (shift_right << 19) | (mask << 24) | (invert << 22), \ 210*4882a593Smuzhiyun .tlv = { .p = (xtlv) } } 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun int snd_wss_info_double(struct snd_kcontrol *kcontrol, 214*4882a593Smuzhiyun struct snd_ctl_elem_info *uinfo); 215*4882a593Smuzhiyun int snd_wss_get_double(struct snd_kcontrol *kcontrol, 216*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol); 217*4882a593Smuzhiyun int snd_wss_put_double(struct snd_kcontrol *kcontrol, 218*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol); 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun #endif /* __SOUND_WSS_H */ 221