1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * wm8960.h -- WM8960 Soc Audio driver platform data 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _WM8960_PDATA_H 7*4882a593Smuzhiyun #define _WM8960_PDATA_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define WM8960_DRES_400R 0 10*4882a593Smuzhiyun #define WM8960_DRES_200R 1 11*4882a593Smuzhiyun #define WM8960_DRES_600R 2 12*4882a593Smuzhiyun #define WM8960_DRES_150R 3 13*4882a593Smuzhiyun #define WM8960_DRES_MAX 3 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct wm8960_data { 16*4882a593Smuzhiyun bool capless; /* Headphone outputs configured in capless mode */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun bool shared_lrclk; /* DAC and ADC LRCLKs are wired together */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Setup for headphone detection 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * hp_cfg[0]: HPSEL[1:0] of R48 (Additional Control 4) 24*4882a593Smuzhiyun * hp_cfg[1]: {HPSWEN:HPSWPOL} of R24 (Additional Control 2). 25*4882a593Smuzhiyun * hp_cfg[2]: {TOCLKSEL:TOEN} of R23 (Additional Control 1). 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun u32 hp_cfg[3]; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Setup for gpio configuration 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * gpio_cfg[0]: ALRCGPIO of R9 (Audio interface) 33*4882a593Smuzhiyun * gpio_cfg[1]: {GPIOPOL:GPIOSEL[2:0]} of R48 (Additional Control 4). 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun u32 gpio_cfg[2]; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif 39