1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or 4*4882a593Smuzhiyun * redistributing this file, you may do so under either license. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright(c) 2018 Intel Corporation. All rights reserved. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __INCLUDE_SOUND_SOF_XTENSA_H__ 10*4882a593Smuzhiyun #define __INCLUDE_SOUND_SOF_XTENSA_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <sound/sof/header.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Architecture specific debug 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Xtensa Firmware Oops data */ 19*4882a593Smuzhiyun struct sof_ipc_dsp_oops_xtensa { 20*4882a593Smuzhiyun struct sof_ipc_dsp_oops_arch_hdr arch_hdr; 21*4882a593Smuzhiyun struct sof_ipc_dsp_oops_plat_hdr plat_hdr; 22*4882a593Smuzhiyun uint32_t exccause; 23*4882a593Smuzhiyun uint32_t excvaddr; 24*4882a593Smuzhiyun uint32_t ps; 25*4882a593Smuzhiyun uint32_t epc1; 26*4882a593Smuzhiyun uint32_t epc2; 27*4882a593Smuzhiyun uint32_t epc3; 28*4882a593Smuzhiyun uint32_t epc4; 29*4882a593Smuzhiyun uint32_t epc5; 30*4882a593Smuzhiyun uint32_t epc6; 31*4882a593Smuzhiyun uint32_t epc7; 32*4882a593Smuzhiyun uint32_t eps2; 33*4882a593Smuzhiyun uint32_t eps3; 34*4882a593Smuzhiyun uint32_t eps4; 35*4882a593Smuzhiyun uint32_t eps5; 36*4882a593Smuzhiyun uint32_t eps6; 37*4882a593Smuzhiyun uint32_t eps7; 38*4882a593Smuzhiyun uint32_t depc; 39*4882a593Smuzhiyun uint32_t intenable; 40*4882a593Smuzhiyun uint32_t interrupt; 41*4882a593Smuzhiyun uint32_t sar; 42*4882a593Smuzhiyun uint32_t debugcause; 43*4882a593Smuzhiyun uint32_t windowbase; 44*4882a593Smuzhiyun uint32_t windowstart; 45*4882a593Smuzhiyun uint32_t excsave1; 46*4882a593Smuzhiyun uint32_t ar[]; 47*4882a593Smuzhiyun } __packed; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #endif 50