1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2019 NXP 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Daniel Baluta <daniel.baluta@nxp.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __INCLUDE_SOUND_SOF_DAI_IMX_H__ 9*4882a593Smuzhiyun #define __INCLUDE_SOUND_SOF_DAI_IMX_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <sound/sof/header.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* ESAI Configuration Request - SOF_IPC_DAI_ESAI_CONFIG */ 14*4882a593Smuzhiyun struct sof_ipc_dai_esai_params { 15*4882a593Smuzhiyun struct sof_ipc_hdr hdr; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* MCLK */ 18*4882a593Smuzhiyun uint16_t reserved1; 19*4882a593Smuzhiyun uint16_t mclk_id; 20*4882a593Smuzhiyun uint32_t mclk_direction; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun uint32_t mclk_rate; /* MCLK frequency in Hz */ 23*4882a593Smuzhiyun uint32_t fsync_rate; /* FSYNC frequency in Hz */ 24*4882a593Smuzhiyun uint32_t bclk_rate; /* BCLK frequency in Hz */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* TDM */ 27*4882a593Smuzhiyun uint32_t tdm_slots; 28*4882a593Smuzhiyun uint32_t rx_slots; 29*4882a593Smuzhiyun uint32_t tx_slots; 30*4882a593Smuzhiyun uint16_t tdm_slot_width; 31*4882a593Smuzhiyun uint16_t reserved2; /* alignment */ 32*4882a593Smuzhiyun } __packed; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* SAI Configuration Request - SOF_IPC_DAI_SAI_CONFIG */ 35*4882a593Smuzhiyun struct sof_ipc_dai_sai_params { 36*4882a593Smuzhiyun struct sof_ipc_hdr hdr; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* MCLK */ 39*4882a593Smuzhiyun uint16_t reserved1; 40*4882a593Smuzhiyun uint16_t mclk_id; 41*4882a593Smuzhiyun uint32_t mclk_direction; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun uint32_t mclk_rate; /* MCLK frequency in Hz */ 44*4882a593Smuzhiyun uint32_t fsync_rate; /* FSYNC frequency in Hz */ 45*4882a593Smuzhiyun uint32_t bclk_rate; /* BCLK frequency in Hz */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* TDM */ 48*4882a593Smuzhiyun uint32_t tdm_slots; 49*4882a593Smuzhiyun uint32_t rx_slots; 50*4882a593Smuzhiyun uint32_t tx_slots; 51*4882a593Smuzhiyun uint16_t tdm_slot_width; 52*4882a593Smuzhiyun uint16_t reserved2; /* alignment */ 53*4882a593Smuzhiyun } __packed; 54*4882a593Smuzhiyun #endif 55