1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * linux/sound/rt5682.h -- Platform data for RT5682 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2018 Realtek Microelectronics 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __LINUX_SND_RT5682_H 9*4882a593Smuzhiyun #define __LINUX_SND_RT5682_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun enum rt5682_dmic1_data_pin { 12*4882a593Smuzhiyun RT5682_DMIC1_NULL, 13*4882a593Smuzhiyun RT5682_DMIC1_DATA_GPIO2, 14*4882a593Smuzhiyun RT5682_DMIC1_DATA_GPIO5, 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun enum rt5682_dmic1_clk_pin { 18*4882a593Smuzhiyun RT5682_DMIC1_CLK_GPIO1, 19*4882a593Smuzhiyun RT5682_DMIC1_CLK_GPIO3, 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun enum rt5682_jd_src { 23*4882a593Smuzhiyun RT5682_JD_NULL, 24*4882a593Smuzhiyun RT5682_JD1, 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun enum rt5682_dai_clks { 28*4882a593Smuzhiyun RT5682_DAI_WCLK_IDX, 29*4882a593Smuzhiyun RT5682_DAI_BCLK_IDX, 30*4882a593Smuzhiyun RT5682_DAI_NUM_CLKS, 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct rt5682_platform_data { 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun int ldo1_en; /* GPIO for LDO1_EN */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun enum rt5682_dmic1_data_pin dmic1_data_pin; 38*4882a593Smuzhiyun enum rt5682_dmic1_clk_pin dmic1_clk_pin; 39*4882a593Smuzhiyun enum rt5682_jd_src jd_src; 40*4882a593Smuzhiyun unsigned int btndet_delay; 41*4882a593Smuzhiyun unsigned int dmic_clk_rate; 42*4882a593Smuzhiyun unsigned int dmic_delay; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun const char *dai_clk_names[RT5682_DAI_NUM_CLKS]; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun 49