1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Platform data for MAX98088 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2010 Maxim Integrated Products 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __SOUND_MAX98088_PDATA_H__ 9*4882a593Smuzhiyun #define __SOUND_MAX98088_PDATA_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Equalizer filter response configuration */ 12*4882a593Smuzhiyun struct max98088_eq_cfg { 13*4882a593Smuzhiyun const char *name; 14*4882a593Smuzhiyun unsigned int rate; 15*4882a593Smuzhiyun u16 band1[5]; 16*4882a593Smuzhiyun u16 band2[5]; 17*4882a593Smuzhiyun u16 band3[5]; 18*4882a593Smuzhiyun u16 band4[5]; 19*4882a593Smuzhiyun u16 band5[5]; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* codec platform data */ 23*4882a593Smuzhiyun struct max98088_pdata { 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Equalizers for DAI1 and DAI2 */ 26*4882a593Smuzhiyun struct max98088_eq_cfg *eq_cfg; 27*4882a593Smuzhiyun unsigned int eq_cfgcnt; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Receiver output can be configured as power amplifier or LINE out */ 30*4882a593Smuzhiyun /* Set receiver_mode to: 31*4882a593Smuzhiyun * 0 = amplifier output, or 32*4882a593Smuzhiyun * 1 = LINE level output 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun unsigned int receiver_mode:1; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Analog/digital microphone configuration: 37*4882a593Smuzhiyun * 0 = analog microphone input (normal setting) 38*4882a593Smuzhiyun * 1 = digital microphone input 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun unsigned int digmic_left_mode:1; 41*4882a593Smuzhiyun unsigned int digmic_right_mode:1; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #endif 46