1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _L3_H_ 3*4882a593Smuzhiyun #define _L3_H_ 1 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun struct l3_pins { 6*4882a593Smuzhiyun void (*setdat)(struct l3_pins *, int); 7*4882a593Smuzhiyun void (*setclk)(struct l3_pins *, int); 8*4882a593Smuzhiyun void (*setmode)(struct l3_pins *, int); 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun int gpio_data; 11*4882a593Smuzhiyun int gpio_clk; 12*4882a593Smuzhiyun int gpio_mode; 13*4882a593Smuzhiyun int use_gpios; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun int data_hold; 16*4882a593Smuzhiyun int data_setup; 17*4882a593Smuzhiyun int clock_high; 18*4882a593Smuzhiyun int mode_hold; 19*4882a593Smuzhiyun int mode; 20*4882a593Smuzhiyun int mode_setup; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct device; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun int l3_write(struct l3_pins *adap, u8 addr, u8 *data, int len); 26*4882a593Smuzhiyun int l3_set_gpio_ops(struct device *dev, struct l3_pins *adap); 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif 29