1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com) 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __SOUND_DESIGNWARE_I2S_H 7*4882a593Smuzhiyun #define __SOUND_DESIGNWARE_I2S_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/dmaengine.h> 10*4882a593Smuzhiyun #include <linux/types.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * struct i2s_clk_config_data - represent i2s clk configuration data 14*4882a593Smuzhiyun * @chan_nr: number of channel 15*4882a593Smuzhiyun * @data_width: number of bits per sample (8/16/24/32 bit) 16*4882a593Smuzhiyun * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz) 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun struct i2s_clk_config_data { 19*4882a593Smuzhiyun int chan_nr; 20*4882a593Smuzhiyun u32 data_width; 21*4882a593Smuzhiyun u32 sample_rate; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct i2s_platform_data { 25*4882a593Smuzhiyun #define DWC_I2S_PLAY (1 << 0) 26*4882a593Smuzhiyun #define DWC_I2S_RECORD (1 << 1) 27*4882a593Smuzhiyun #define DW_I2S_SLAVE (1 << 2) 28*4882a593Smuzhiyun #define DW_I2S_MASTER (1 << 3) 29*4882a593Smuzhiyun unsigned int cap; 30*4882a593Smuzhiyun int channel; 31*4882a593Smuzhiyun u32 snd_fmts; 32*4882a593Smuzhiyun u32 snd_rates; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0) 35*4882a593Smuzhiyun #define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1) 36*4882a593Smuzhiyun #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2) 37*4882a593Smuzhiyun unsigned int quirks; 38*4882a593Smuzhiyun unsigned int i2s_reg_comp1; 39*4882a593Smuzhiyun unsigned int i2s_reg_comp2; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun void *play_dma_data; 42*4882a593Smuzhiyun void *capture_dma_data; 43*4882a593Smuzhiyun bool (*filter)(struct dma_chan *chan, void *slave); 44*4882a593Smuzhiyun int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun struct i2s_dma_data { 48*4882a593Smuzhiyun void *data; 49*4882a593Smuzhiyun dma_addr_t addr; 50*4882a593Smuzhiyun u32 max_burst; 51*4882a593Smuzhiyun enum dma_slave_buswidth addr_width; 52*4882a593Smuzhiyun bool (*filter)(struct dma_chan *chan, void *slave); 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* I2S DMA registers */ 56*4882a593Smuzhiyun #define I2S_RXDMA 0x01C0 57*4882a593Smuzhiyun #define I2S_TXDMA 0x01C8 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */ 60*4882a593Smuzhiyun #define FOUR_CHANNEL_SUPPORT 4 /* up to 3.1 */ 61*4882a593Smuzhiyun #define SIX_CHANNEL_SUPPORT 6 /* up to 5.1 */ 62*4882a593Smuzhiyun #define EIGHT_CHANNEL_SUPPORT 8 /* up to 7.1 */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif /* __SOUND_DESIGNWARE_I2S_H */ 65