1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun #ifndef __SOUND_CS4231_REGS_H 3*4882a593Smuzhiyun #define __SOUND_CS4231_REGS_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* 6*4882a593Smuzhiyun * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 7*4882a593Smuzhiyun * Definitions for CS4231 & InterWave chips & compatible chips registers 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* IO ports */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define CS4231P(x) (c_d_c_CS4231##x) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define c_d_c_CS4231REGSEL 0 15*4882a593Smuzhiyun #define c_d_c_CS4231REG 1 16*4882a593Smuzhiyun #define c_d_c_CS4231STATUS 2 17*4882a593Smuzhiyun #define c_d_c_CS4231PIO 3 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* codec registers */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define CS4231_LEFT_INPUT 0x00 /* left input control */ 22*4882a593Smuzhiyun #define CS4231_RIGHT_INPUT 0x01 /* right input control */ 23*4882a593Smuzhiyun #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */ 24*4882a593Smuzhiyun #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */ 25*4882a593Smuzhiyun #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */ 26*4882a593Smuzhiyun #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */ 27*4882a593Smuzhiyun #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */ 28*4882a593Smuzhiyun #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */ 29*4882a593Smuzhiyun #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */ 30*4882a593Smuzhiyun #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */ 31*4882a593Smuzhiyun #define CS4231_PIN_CTRL 0x0a /* pin control */ 32*4882a593Smuzhiyun #define CS4231_TEST_INIT 0x0b /* test and initialization */ 33*4882a593Smuzhiyun #define CS4231_MISC_INFO 0x0c /* miscellaneous information */ 34*4882a593Smuzhiyun #define CS4231_LOOPBACK 0x0d /* loopback control */ 35*4882a593Smuzhiyun #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */ 36*4882a593Smuzhiyun #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */ 37*4882a593Smuzhiyun #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */ 38*4882a593Smuzhiyun #define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */ 39*4882a593Smuzhiyun #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */ 40*4882a593Smuzhiyun #define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */ 41*4882a593Smuzhiyun #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */ 42*4882a593Smuzhiyun #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */ 43*4882a593Smuzhiyun #define CS4231_TIMER_LOW 0x14 /* timer low byte */ 44*4882a593Smuzhiyun #define CS4231_TIMER_HIGH 0x15 /* timer high byte */ 45*4882a593Smuzhiyun #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */ 46*4882a593Smuzhiyun #define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */ 47*4882a593Smuzhiyun #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */ 48*4882a593Smuzhiyun #define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */ 49*4882a593Smuzhiyun #define CS4236_EXT_REG 0x17 /* extended register access */ 50*4882a593Smuzhiyun #define CS4231_IRQ_STATUS 0x18 /* irq status register */ 51*4882a593Smuzhiyun #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */ 52*4882a593Smuzhiyun #define CS4231_VERSION 0x19 /* CS4231(A) - version values */ 53*4882a593Smuzhiyun #define CS4231_MONO_CTRL 0x1a /* mono input/output control */ 54*4882a593Smuzhiyun #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */ 55*4882a593Smuzhiyun #define AD1845_PWR_DOWN 0x1b /* power down control */ 56*4882a593Smuzhiyun #define CS4235_LEFT_MASTER 0x1b /* left master output control */ 57*4882a593Smuzhiyun #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */ 58*4882a593Smuzhiyun #define AD1845_CLOCK 0x1d /* crystal clock select and total power down */ 59*4882a593Smuzhiyun #define CS4235_RIGHT_MASTER 0x1d /* right master output control */ 60*4882a593Smuzhiyun #define CS4231_REC_UPR_CNT 0x1e /* record upper count */ 61*4882a593Smuzhiyun #define CS4231_REC_LWR_CNT 0x1f /* record lower count */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* definitions for codec register select port - CODECP( REGSEL ) */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define CS4231_INIT 0x80 /* CODEC is initializing */ 66*4882a593Smuzhiyun #define CS4231_MCE 0x40 /* mode change enable */ 67*4882a593Smuzhiyun #define CS4231_TRD 0x20 /* transfer request disable */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* definitions for codec status register - CODECP( STATUS ) */ 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* definitions for codec irq status */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define CS4231_PLAYBACK_IRQ 0x10 76*4882a593Smuzhiyun #define CS4231_RECORD_IRQ 0x20 77*4882a593Smuzhiyun #define CS4231_TIMER_IRQ 0x40 78*4882a593Smuzhiyun #define CS4231_ALL_IRQS 0x70 79*4882a593Smuzhiyun #define CS4231_REC_UNDERRUN 0x08 80*4882a593Smuzhiyun #define CS4231_REC_OVERRUN 0x04 81*4882a593Smuzhiyun #define CS4231_PLY_OVERRUN 0x02 82*4882a593Smuzhiyun #define CS4231_PLY_UNDERRUN 0x01 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */ 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define CS4231_ENABLE_MIC_GAIN 0x20 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define CS4231_MIXS_LINE 0x00 89*4882a593Smuzhiyun #define CS4231_MIXS_AUX1 0x40 90*4882a593Smuzhiyun #define CS4231_MIXS_MIC 0x80 91*4882a593Smuzhiyun #define CS4231_MIXS_ALL 0xc0 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */ 96*4882a593Smuzhiyun #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */ 97*4882a593Smuzhiyun #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */ 98*4882a593Smuzhiyun #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */ 99*4882a593Smuzhiyun #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */ 100*4882a593Smuzhiyun #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */ 101*4882a593Smuzhiyun #define CS4231_STEREO 0x10 /* stereo mode */ 102*4882a593Smuzhiyun /* bits 3-1 define frequency divisor */ 103*4882a593Smuzhiyun #define CS4231_XTAL1 0x00 /* 24.576 crystal */ 104*4882a593Smuzhiyun #define CS4231_XTAL2 0x01 /* 16.9344 crystal */ 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* definitions for interface control register - CS4231_IFACE_CTRL */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define CS4231_RECORD_PIO 0x80 /* record PIO enable */ 109*4882a593Smuzhiyun #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */ 110*4882a593Smuzhiyun #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */ 111*4882a593Smuzhiyun #define CS4231_AUTOCALIB 0x08 /* auto calibrate */ 112*4882a593Smuzhiyun #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */ 113*4882a593Smuzhiyun #define CS4231_RECORD_ENABLE 0x02 /* record enable */ 114*4882a593Smuzhiyun #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* definitions for pin control register - CS4231_PIN_CTRL */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */ 119*4882a593Smuzhiyun #define CS4231_XCTL1 0x40 /* external control #1 */ 120*4882a593Smuzhiyun #define CS4231_XCTL0 0x80 /* external control #0 */ 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* definitions for test and init register - CS4231_TEST_INIT */ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */ 125*4882a593Smuzhiyun #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* definitions for misc control register - CS4231_MISC_INFO */ 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define CS4231_MODE2 0x40 /* MODE 2 */ 130*4882a593Smuzhiyun #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */ 131*4882a593Smuzhiyun #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */ 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define CS4231_DACZ 0x01 /* zero DAC when underrun */ 136*4882a593Smuzhiyun #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */ 137*4882a593Smuzhiyun #define CS4231_OLB 0x80 /* output level bit */ 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /* definitions for Extended Registers - CS4236+ */ 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f)) 142*4882a593Smuzhiyun #define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */ 145*4882a593Smuzhiyun #define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */ 146*4882a593Smuzhiyun #define CS4236_LEFT_MIC 0x28 /* left MIC volume */ 147*4882a593Smuzhiyun #define CS4236_RIGHT_MIC 0x38 /* right MIC volume */ 148*4882a593Smuzhiyun #define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */ 149*4882a593Smuzhiyun #define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */ 150*4882a593Smuzhiyun #define CS4236_LEFT_FM 0x68 /* left FM volume */ 151*4882a593Smuzhiyun #define CS4236_RIGHT_FM 0x78 /* right FM volume */ 152*4882a593Smuzhiyun #define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */ 153*4882a593Smuzhiyun #define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */ 154*4882a593Smuzhiyun #define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */ 155*4882a593Smuzhiyun #define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */ 156*4882a593Smuzhiyun #define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */ 157*4882a593Smuzhiyun #define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */ 158*4882a593Smuzhiyun #define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */ 159*4882a593Smuzhiyun #define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */ 160*4882a593Smuzhiyun #define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */ 161*4882a593Smuzhiyun #define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */ 162*4882a593Smuzhiyun #define CS4236_VERSION 0x9c /* chip version and ID */ 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* definitions for extended registers - OPTI93X */ 165*4882a593Smuzhiyun #define OPTi931_AUX_LEFT_INPUT 0x10 166*4882a593Smuzhiyun #define OPTi931_AUX_RIGHT_INPUT 0x11 167*4882a593Smuzhiyun #define OPTi93X_MIC_LEFT_INPUT 0x14 168*4882a593Smuzhiyun #define OPTi93X_MIC_RIGHT_INPUT 0x15 169*4882a593Smuzhiyun #define OPTi93X_OUT_LEFT 0x16 170*4882a593Smuzhiyun #define OPTi93X_OUT_RIGHT 0x17 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #endif /* __SOUND_CS4231_REGS_H */ 173