1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _ACI_H_ 3*4882a593Smuzhiyun #define _ACI_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define ACI_REG_COMMAND 0 /* write register offset */ 6*4882a593Smuzhiyun #define ACI_REG_STATUS 1 /* read register offset */ 7*4882a593Smuzhiyun #define ACI_REG_BUSY 2 /* busy register offset */ 8*4882a593Smuzhiyun #define ACI_REG_RDS 2 /* PCM20: RDS register offset */ 9*4882a593Smuzhiyun #define ACI_MINTIME 500 /* ACI time out limit */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define ACI_SET_MUTE 0x0d 12*4882a593Smuzhiyun #define ACI_SET_POWERAMP 0x0f 13*4882a593Smuzhiyun #define ACI_SET_TUNERMUTE 0xa3 14*4882a593Smuzhiyun #define ACI_SET_TUNERMONO 0xa4 15*4882a593Smuzhiyun #define ACI_SET_IDE 0xd0 16*4882a593Smuzhiyun #define ACI_SET_WSS 0xd1 17*4882a593Smuzhiyun #define ACI_SET_SOLOMODE 0xd2 18*4882a593Smuzhiyun #define ACI_SET_PREAMP 0x03 19*4882a593Smuzhiyun #define ACI_GET_PREAMP 0x21 20*4882a593Smuzhiyun #define ACI_WRITE_TUNE 0xa7 21*4882a593Smuzhiyun #define ACI_READ_TUNERSTEREO 0xa8 22*4882a593Smuzhiyun #define ACI_READ_TUNERSTATION 0xa9 23*4882a593Smuzhiyun #define ACI_READ_VERSION 0xf1 24*4882a593Smuzhiyun #define ACI_READ_IDCODE 0xf2 25*4882a593Smuzhiyun #define ACI_INIT 0xff 26*4882a593Smuzhiyun #define ACI_STATUS 0xf0 27*4882a593Smuzhiyun #define ACI_S_GENERAL 0x00 28*4882a593Smuzhiyun #define ACI_ERROR_OP 0xdf 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* ACI Mixer */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* These are the values for the right channel GET registers. 33*4882a593Smuzhiyun Add an offset of 0x01 for the left channel register. 34*4882a593Smuzhiyun (left=right+0x01) */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define ACI_GET_MASTER 0x03 37*4882a593Smuzhiyun #define ACI_GET_MIC 0x05 38*4882a593Smuzhiyun #define ACI_GET_LINE 0x07 39*4882a593Smuzhiyun #define ACI_GET_CD 0x09 40*4882a593Smuzhiyun #define ACI_GET_SYNTH 0x0b 41*4882a593Smuzhiyun #define ACI_GET_PCM 0x0d 42*4882a593Smuzhiyun #define ACI_GET_LINE1 0x10 /* Radio on PCM20 */ 43*4882a593Smuzhiyun #define ACI_GET_LINE2 0x12 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define ACI_GET_EQ1 0x22 /* from Bass ... */ 46*4882a593Smuzhiyun #define ACI_GET_EQ2 0x24 47*4882a593Smuzhiyun #define ACI_GET_EQ3 0x26 48*4882a593Smuzhiyun #define ACI_GET_EQ4 0x28 49*4882a593Smuzhiyun #define ACI_GET_EQ5 0x2a 50*4882a593Smuzhiyun #define ACI_GET_EQ6 0x2c 51*4882a593Smuzhiyun #define ACI_GET_EQ7 0x2e /* ... to Treble */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* And these are the values for the right channel SET registers. 54*4882a593Smuzhiyun For left channel access you have to add an offset of 0x08. 55*4882a593Smuzhiyun MASTER is an exception, which needs an offset of 0x01 */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define ACI_SET_MASTER 0x00 58*4882a593Smuzhiyun #define ACI_SET_MIC 0x30 59*4882a593Smuzhiyun #define ACI_SET_LINE 0x31 60*4882a593Smuzhiyun #define ACI_SET_CD 0x34 61*4882a593Smuzhiyun #define ACI_SET_SYNTH 0x33 62*4882a593Smuzhiyun #define ACI_SET_PCM 0x32 63*4882a593Smuzhiyun #define ACI_SET_LINE1 0x35 /* Radio on PCM20 */ 64*4882a593Smuzhiyun #define ACI_SET_LINE2 0x36 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define ACI_SET_EQ1 0x40 /* from Bass ... */ 67*4882a593Smuzhiyun #define ACI_SET_EQ2 0x41 68*4882a593Smuzhiyun #define ACI_SET_EQ3 0x42 69*4882a593Smuzhiyun #define ACI_SET_EQ4 0x43 70*4882a593Smuzhiyun #define ACI_SET_EQ5 0x44 71*4882a593Smuzhiyun #define ACI_SET_EQ6 0x45 72*4882a593Smuzhiyun #define ACI_SET_EQ7 0x46 /* ... to Treble */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun struct snd_miro_aci { 75*4882a593Smuzhiyun unsigned long aci_port; 76*4882a593Smuzhiyun int aci_vendor; 77*4882a593Smuzhiyun int aci_product; 78*4882a593Smuzhiyun int aci_version; 79*4882a593Smuzhiyun int aci_amp; 80*4882a593Smuzhiyun int aci_preamp; 81*4882a593Smuzhiyun int aci_solomode; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun struct mutex aci_mutex; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun int snd_aci_cmd(struct snd_miro_aci *aci, int write1, int write2, int write3); 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct snd_miro_aci *snd_aci_get_aci(void); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* _ACI_H_ */ 91*4882a593Smuzhiyun 92