xref: /OK3568_Linux_fs/kernel/include/soc/tegra/mc.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2014 NVIDIA Corporation
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef __SOC_TEGRA_MC_H__
7*4882a593Smuzhiyun #define __SOC_TEGRA_MC_H__
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/reset-controller.h>
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun struct clk;
14*4882a593Smuzhiyun struct device;
15*4882a593Smuzhiyun struct page;
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun struct tegra_smmu_enable {
18*4882a593Smuzhiyun 	unsigned int reg;
19*4882a593Smuzhiyun 	unsigned int bit;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun struct tegra_mc_timing {
23*4882a593Smuzhiyun 	unsigned long rate;
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun 	u32 *emem_data;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /* latency allowance */
29*4882a593Smuzhiyun struct tegra_mc_la {
30*4882a593Smuzhiyun 	unsigned int reg;
31*4882a593Smuzhiyun 	unsigned int shift;
32*4882a593Smuzhiyun 	unsigned int mask;
33*4882a593Smuzhiyun 	unsigned int def;
34*4882a593Smuzhiyun };
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun struct tegra_mc_client {
37*4882a593Smuzhiyun 	unsigned int id;
38*4882a593Smuzhiyun 	const char *name;
39*4882a593Smuzhiyun 	unsigned int swgroup;
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	unsigned int fifo_size;
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	struct tegra_smmu_enable smmu;
44*4882a593Smuzhiyun 	struct tegra_mc_la la;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun struct tegra_smmu_swgroup {
48*4882a593Smuzhiyun 	const char *name;
49*4882a593Smuzhiyun 	unsigned int swgroup;
50*4882a593Smuzhiyun 	unsigned int reg;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun struct tegra_smmu_group_soc {
54*4882a593Smuzhiyun 	const char *name;
55*4882a593Smuzhiyun 	const unsigned int *swgroups;
56*4882a593Smuzhiyun 	unsigned int num_swgroups;
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun struct tegra_smmu_soc {
60*4882a593Smuzhiyun 	const struct tegra_mc_client *clients;
61*4882a593Smuzhiyun 	unsigned int num_clients;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	const struct tegra_smmu_swgroup *swgroups;
64*4882a593Smuzhiyun 	unsigned int num_swgroups;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	const struct tegra_smmu_group_soc *groups;
67*4882a593Smuzhiyun 	unsigned int num_groups;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	bool supports_round_robin_arbitration;
70*4882a593Smuzhiyun 	bool supports_request_limit;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	unsigned int num_tlb_lines;
73*4882a593Smuzhiyun 	unsigned int num_asids;
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun struct tegra_mc;
77*4882a593Smuzhiyun struct tegra_smmu;
78*4882a593Smuzhiyun struct gart_device;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun #ifdef CONFIG_TEGRA_IOMMU_SMMU
81*4882a593Smuzhiyun struct tegra_smmu *tegra_smmu_probe(struct device *dev,
82*4882a593Smuzhiyun 				    const struct tegra_smmu_soc *soc,
83*4882a593Smuzhiyun 				    struct tegra_mc *mc);
84*4882a593Smuzhiyun void tegra_smmu_remove(struct tegra_smmu *smmu);
85*4882a593Smuzhiyun #else
86*4882a593Smuzhiyun static inline struct tegra_smmu *
tegra_smmu_probe(struct device * dev,const struct tegra_smmu_soc * soc,struct tegra_mc * mc)87*4882a593Smuzhiyun tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
88*4882a593Smuzhiyun 		 struct tegra_mc *mc)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 	return NULL;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun 
tegra_smmu_remove(struct tegra_smmu * smmu)93*4882a593Smuzhiyun static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun #endif
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #ifdef CONFIG_TEGRA_IOMMU_GART
99*4882a593Smuzhiyun struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc);
100*4882a593Smuzhiyun int tegra_gart_suspend(struct gart_device *gart);
101*4882a593Smuzhiyun int tegra_gart_resume(struct gart_device *gart);
102*4882a593Smuzhiyun #else
103*4882a593Smuzhiyun static inline struct gart_device *
tegra_gart_probe(struct device * dev,struct tegra_mc * mc)104*4882a593Smuzhiyun tegra_gart_probe(struct device *dev, struct tegra_mc *mc)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	return ERR_PTR(-ENODEV);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
tegra_gart_suspend(struct gart_device * gart)109*4882a593Smuzhiyun static inline int tegra_gart_suspend(struct gart_device *gart)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	return -ENODEV;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun 
tegra_gart_resume(struct gart_device * gart)114*4882a593Smuzhiyun static inline int tegra_gart_resume(struct gart_device *gart)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	return -ENODEV;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun #endif
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun struct tegra_mc_reset {
121*4882a593Smuzhiyun 	const char *name;
122*4882a593Smuzhiyun 	unsigned long id;
123*4882a593Smuzhiyun 	unsigned int control;
124*4882a593Smuzhiyun 	unsigned int status;
125*4882a593Smuzhiyun 	unsigned int reset;
126*4882a593Smuzhiyun 	unsigned int bit;
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun struct tegra_mc_reset_ops {
130*4882a593Smuzhiyun 	int (*hotreset_assert)(struct tegra_mc *mc,
131*4882a593Smuzhiyun 			       const struct tegra_mc_reset *rst);
132*4882a593Smuzhiyun 	int (*hotreset_deassert)(struct tegra_mc *mc,
133*4882a593Smuzhiyun 				 const struct tegra_mc_reset *rst);
134*4882a593Smuzhiyun 	int (*block_dma)(struct tegra_mc *mc,
135*4882a593Smuzhiyun 			 const struct tegra_mc_reset *rst);
136*4882a593Smuzhiyun 	bool (*dma_idling)(struct tegra_mc *mc,
137*4882a593Smuzhiyun 			   const struct tegra_mc_reset *rst);
138*4882a593Smuzhiyun 	int (*unblock_dma)(struct tegra_mc *mc,
139*4882a593Smuzhiyun 			   const struct tegra_mc_reset *rst);
140*4882a593Smuzhiyun 	int (*reset_status)(struct tegra_mc *mc,
141*4882a593Smuzhiyun 			    const struct tegra_mc_reset *rst);
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun struct tegra_mc_soc {
145*4882a593Smuzhiyun 	const struct tegra_mc_client *clients;
146*4882a593Smuzhiyun 	unsigned int num_clients;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	const unsigned long *emem_regs;
149*4882a593Smuzhiyun 	unsigned int num_emem_regs;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	unsigned int num_address_bits;
152*4882a593Smuzhiyun 	unsigned int atom_size;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	u8 client_id_mask;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	const struct tegra_smmu_soc *smmu;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	u32 intmask;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	const struct tegra_mc_reset_ops *reset_ops;
161*4882a593Smuzhiyun 	const struct tegra_mc_reset *resets;
162*4882a593Smuzhiyun 	unsigned int num_resets;
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun struct tegra_mc {
166*4882a593Smuzhiyun 	struct device *dev;
167*4882a593Smuzhiyun 	struct tegra_smmu *smmu;
168*4882a593Smuzhiyun 	struct gart_device *gart;
169*4882a593Smuzhiyun 	void __iomem *regs;
170*4882a593Smuzhiyun 	struct clk *clk;
171*4882a593Smuzhiyun 	int irq;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	const struct tegra_mc_soc *soc;
174*4882a593Smuzhiyun 	unsigned long tick;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	struct tegra_mc_timing *timings;
177*4882a593Smuzhiyun 	unsigned int num_timings;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	struct reset_controller_dev reset;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	spinlock_t lock;
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
185*4882a593Smuzhiyun unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun #endif /* __SOC_TEGRA_MC_H__ */
188