1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __SOC_TEGRA_FUSE_H__ 7*4882a593Smuzhiyun #define __SOC_TEGRA_FUSE_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define TEGRA20 0x20 10*4882a593Smuzhiyun #define TEGRA30 0x30 11*4882a593Smuzhiyun #define TEGRA114 0x35 12*4882a593Smuzhiyun #define TEGRA124 0x40 13*4882a593Smuzhiyun #define TEGRA132 0x13 14*4882a593Smuzhiyun #define TEGRA210 0x21 15*4882a593Smuzhiyun #define TEGRA186 0x18 16*4882a593Smuzhiyun #define TEGRA194 0x19 17*4882a593Smuzhiyun #define TEGRA234 0x23 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define TEGRA_FUSE_SKU_CALIB_0 0xf0 20*4882a593Smuzhiyun #define TEGRA30_FUSE_SATA_CALIB 0x124 21*4882a593Smuzhiyun #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun u32 tegra_read_chipid(void); 26*4882a593Smuzhiyun u8 tegra_get_chip_id(void); 27*4882a593Smuzhiyun u8 tegra_get_platform(void); 28*4882a593Smuzhiyun bool tegra_is_silicon(void); 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun enum tegra_revision { 31*4882a593Smuzhiyun TEGRA_REVISION_UNKNOWN = 0, 32*4882a593Smuzhiyun TEGRA_REVISION_A01, 33*4882a593Smuzhiyun TEGRA_REVISION_A02, 34*4882a593Smuzhiyun TEGRA_REVISION_A03, 35*4882a593Smuzhiyun TEGRA_REVISION_A03p, 36*4882a593Smuzhiyun TEGRA_REVISION_A04, 37*4882a593Smuzhiyun TEGRA_REVISION_MAX, 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct tegra_sku_info { 41*4882a593Smuzhiyun int sku_id; 42*4882a593Smuzhiyun int cpu_process_id; 43*4882a593Smuzhiyun int cpu_speedo_id; 44*4882a593Smuzhiyun int cpu_speedo_value; 45*4882a593Smuzhiyun int cpu_iddq_value; 46*4882a593Smuzhiyun int soc_process_id; 47*4882a593Smuzhiyun int soc_speedo_id; 48*4882a593Smuzhiyun int soc_speedo_value; 49*4882a593Smuzhiyun int gpu_process_id; 50*4882a593Smuzhiyun int gpu_speedo_id; 51*4882a593Smuzhiyun int gpu_speedo_value; 52*4882a593Smuzhiyun enum tegra_revision revision; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun u32 tegra_read_straps(void); 56*4882a593Smuzhiyun u32 tegra_read_ram_code(void); 57*4882a593Smuzhiyun int tegra_fuse_readl(unsigned long offset, u32 *value); 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun extern struct tegra_sku_info tegra_sku_info; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun struct device *tegra_soc_device_register(void); 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #endif /* __ASSEMBLY__ */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #endif /* __SOC_TEGRA_FUSE_H__ */ 66