1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Functions and macros to control the flowcontroller 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __SOC_TEGRA_FLOWCTRL_H__ 9*4882a593Smuzhiyun #define __SOC_TEGRA_FLOWCTRL_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 12*4882a593Smuzhiyun #define FLOW_CTRL_WAITEVENT (2 << 29) 13*4882a593Smuzhiyun #define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) 14*4882a593Smuzhiyun #define FLOW_CTRL_JTAG_RESUME (1 << 28) 15*4882a593Smuzhiyun #define FLOW_CTRL_SCLK_RESUME (1 << 27) 16*4882a593Smuzhiyun #define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) 17*4882a593Smuzhiyun #define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) 18*4882a593Smuzhiyun #define FLOW_CTRL_HALT_LIC_IRQ (1 << 11) 19*4882a593Smuzhiyun #define FLOW_CTRL_HALT_LIC_FIQ (1 << 10) 20*4882a593Smuzhiyun #define FLOW_CTRL_HALT_GIC_IRQ (1 << 9) 21*4882a593Smuzhiyun #define FLOW_CTRL_HALT_GIC_FIQ (1 << 8) 22*4882a593Smuzhiyun #define FLOW_CTRL_CPU0_CSR 0x8 23*4882a593Smuzhiyun #define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) 24*4882a593Smuzhiyun #define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) 25*4882a593Smuzhiyun #define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13) 26*4882a593Smuzhiyun #define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12) 27*4882a593Smuzhiyun #define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \ 28*4882a593Smuzhiyun FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \ 29*4882a593Smuzhiyun FLOW_CTRL_CSR_ENABLE_EXT_CRAIL) 30*4882a593Smuzhiyun #define FLOW_CTRL_CSR_ENABLE (1 << 0) 31*4882a593Smuzhiyun #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 32*4882a593Smuzhiyun #define FLOW_CTRL_CPU1_CSR 0x18 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 (1 << 4) 35*4882a593Smuzhiyun #define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP (3 << 4) 36*4882a593Smuzhiyun #define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP 0 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 (1 << 8) 39*4882a593Smuzhiyun #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP (0xF << 4) 40*4882a593Smuzhiyun #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP (0xF << 8) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 43*4882a593Smuzhiyun #ifdef CONFIG_SOC_TEGRA_FLOWCTRL 44*4882a593Smuzhiyun u32 flowctrl_read_cpu_csr(unsigned int cpuid); 45*4882a593Smuzhiyun void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value); 46*4882a593Smuzhiyun void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun void flowctrl_cpu_suspend_enter(unsigned int cpuid); 49*4882a593Smuzhiyun void flowctrl_cpu_suspend_exit(unsigned int cpuid); 50*4882a593Smuzhiyun #else flowctrl_read_cpu_csr(unsigned int cpuid)51*4882a593Smuzhiyunstatic inline u32 flowctrl_read_cpu_csr(unsigned int cpuid) 52*4882a593Smuzhiyun { 53*4882a593Smuzhiyun return 0; 54*4882a593Smuzhiyun } 55*4882a593Smuzhiyun flowctrl_write_cpu_csr(unsigned int cpuid,u32 value)56*4882a593Smuzhiyunstatic inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value) 57*4882a593Smuzhiyun { 58*4882a593Smuzhiyun } 59*4882a593Smuzhiyun flowctrl_write_cpu_halt(unsigned int cpuid,u32 value)60*4882a593Smuzhiyunstatic inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {} 61*4882a593Smuzhiyun flowctrl_cpu_suspend_enter(unsigned int cpuid)62*4882a593Smuzhiyunstatic inline void flowctrl_cpu_suspend_enter(unsigned int cpuid) 63*4882a593Smuzhiyun { 64*4882a593Smuzhiyun } 65*4882a593Smuzhiyun flowctrl_cpu_suspend_exit(unsigned int cpuid)66*4882a593Smuzhiyunstatic inline void flowctrl_cpu_suspend_exit(unsigned int cpuid) 67*4882a593Smuzhiyun { 68*4882a593Smuzhiyun } 69*4882a593Smuzhiyun #endif /* CONFIG_SOC_TEGRA_FLOWCTRL */ 70*4882a593Smuzhiyun #endif /* __ASSEMBLY */ 71*4882a593Smuzhiyun #endif /* __SOC_TEGRA_FLOWCTRL_H__ */ 72