1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun * Author: Lin Huang <hl@rock-chips.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun #ifndef __SOC_ROCKCHIP_SIP_H 7*4882a593Smuzhiyun #define __SOC_ROCKCHIP_SIP_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define ROCKCHIP_SIP_DRAM_FREQ 0x82000008 10*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00 11*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01 12*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE 0x02 13*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR 0x03 14*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_GET_BW 0x04 15*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05 16*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 17*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 18*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08 19*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE 0x09 20*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL 0x0a 21*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_DEBUG 0x0b 22*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_MCU_START 0x0c 23*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_GET_FREQ_INFO 0x0e 24*4882a593Smuzhiyun #define ROCKCHIP_SIP_CONFIG_DRAM_ADDRMAP_GET 0x10 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #endif 27