1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 5*4882a593Smuzhiyun * under the terms and conditions of the GNU General Public License, 6*4882a593Smuzhiyun * version 2, as published by the Free Software Foundation. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This program is distributed in the hope it will be useful, but WITHOUT 9*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11*4882a593Smuzhiyun * more details. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #ifndef __SOC_ROCKCHIP_DMC_H 14*4882a593Smuzhiyun #define __SOC_ROCKCHIP_DMC_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <linux/devfreq.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* for lcdc_type */ 19*4882a593Smuzhiyun #define SCREEN_NULL 0 20*4882a593Smuzhiyun #define SCREEN_RGB 1 21*4882a593Smuzhiyun #define SCREEN_LVDS 2 22*4882a593Smuzhiyun #define SCREEN_DUAL_LVDS 3 23*4882a593Smuzhiyun #define SCREEN_MCU 4 24*4882a593Smuzhiyun #define SCREEN_TVOUT 5 25*4882a593Smuzhiyun #define SCREEN_HDMI 6 26*4882a593Smuzhiyun #define SCREEN_MIPI 7 27*4882a593Smuzhiyun #define SCREEN_DUAL_MIPI 8 28*4882a593Smuzhiyun #define SCREEN_EDP 9 29*4882a593Smuzhiyun #define SCREEN_TVOUT_TEST 10 30*4882a593Smuzhiyun #define SCREEN_LVDS_10BIT 11 31*4882a593Smuzhiyun #define SCREEN_DUAL_LVDS_10BIT 12 32*4882a593Smuzhiyun #define SCREEN_DP 13 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define DMCFREQ_TABLE_END ~1u 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct freq_map_table { 37*4882a593Smuzhiyun unsigned int min; 38*4882a593Smuzhiyun unsigned int max; 39*4882a593Smuzhiyun unsigned long freq; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct rl_map_table { 43*4882a593Smuzhiyun unsigned int pn; /* panel number */ 44*4882a593Smuzhiyun unsigned int rl; /* readlatency */ 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun struct dmcfreq_common_info { 48*4882a593Smuzhiyun struct device *dev; 49*4882a593Smuzhiyun struct devfreq *devfreq; 50*4882a593Smuzhiyun struct freq_map_table *vop_bw_tbl; 51*4882a593Smuzhiyun struct freq_map_table *vop_frame_bw_tbl; 52*4882a593Smuzhiyun struct rl_map_table *vop_pn_rl_tbl; 53*4882a593Smuzhiyun struct delayed_work msch_rl_work; 54*4882a593Smuzhiyun unsigned long vop_4k_rate; 55*4882a593Smuzhiyun unsigned long vop_req_rate; 56*4882a593Smuzhiyun unsigned int read_latency; 57*4882a593Smuzhiyun unsigned int auto_freq_en; 58*4882a593Smuzhiyun bool is_msch_rl_work_started; 59*4882a593Smuzhiyun int (*set_msch_readlatency)(unsigned int rl); 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct dmcfreq_vop_info { 63*4882a593Smuzhiyun unsigned int line_bw_mbyte; 64*4882a593Smuzhiyun unsigned int frame_bw_mbyte; 65*4882a593Smuzhiyun unsigned int plane_num; 66*4882a593Smuzhiyun unsigned int plane_num_4k; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #if IS_REACHABLE(CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ) 70*4882a593Smuzhiyun void rockchip_dmcfreq_lock(void); 71*4882a593Smuzhiyun void rockchip_dmcfreq_lock_nested(void); 72*4882a593Smuzhiyun void rockchip_dmcfreq_unlock(void); 73*4882a593Smuzhiyun int rockchip_dmcfreq_write_trylock(void); 74*4882a593Smuzhiyun void rockchip_dmcfreq_write_unlock(void); 75*4882a593Smuzhiyun int rockchip_dmcfreq_wait_complete(void); 76*4882a593Smuzhiyun int rockchip_dmcfreq_vop_bandwidth_init(struct dmcfreq_common_info *info); 77*4882a593Smuzhiyun int rockchip_dmcfreq_vop_bandwidth_request(struct dmcfreq_vop_info *vop_info); 78*4882a593Smuzhiyun void rockchip_dmcfreq_vop_bandwidth_update(struct dmcfreq_vop_info *vop_info); 79*4882a593Smuzhiyun #else rockchip_dmcfreq_lock(void)80*4882a593Smuzhiyunstatic inline void rockchip_dmcfreq_lock(void) 81*4882a593Smuzhiyun { 82*4882a593Smuzhiyun } 83*4882a593Smuzhiyun rockchip_dmcfreq_lock_nested(void)84*4882a593Smuzhiyunstatic inline void rockchip_dmcfreq_lock_nested(void) 85*4882a593Smuzhiyun { 86*4882a593Smuzhiyun } 87*4882a593Smuzhiyun rockchip_dmcfreq_unlock(void)88*4882a593Smuzhiyunstatic inline void rockchip_dmcfreq_unlock(void) 89*4882a593Smuzhiyun { 90*4882a593Smuzhiyun } 91*4882a593Smuzhiyun rockchip_dmcfreq_write_trylock(void)92*4882a593Smuzhiyunstatic inline int rockchip_dmcfreq_write_trylock(void) 93*4882a593Smuzhiyun { 94*4882a593Smuzhiyun return 0; 95*4882a593Smuzhiyun } 96*4882a593Smuzhiyun rockchip_dmcfreq_write_unlock(void)97*4882a593Smuzhiyunstatic inline void rockchip_dmcfreq_write_unlock(void) 98*4882a593Smuzhiyun { 99*4882a593Smuzhiyun } 100*4882a593Smuzhiyun rockchip_dmcfreq_wait_complete(void)101*4882a593Smuzhiyunstatic inline int rockchip_dmcfreq_wait_complete(void) 102*4882a593Smuzhiyun { 103*4882a593Smuzhiyun return 0; 104*4882a593Smuzhiyun } 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun static inline int rockchip_dmcfreq_vop_bandwidth_request(struct dmcfreq_vop_info * vop_info)107*4882a593Smuzhiyunrockchip_dmcfreq_vop_bandwidth_request(struct dmcfreq_vop_info *vop_info) 108*4882a593Smuzhiyun { 109*4882a593Smuzhiyun return 0; 110*4882a593Smuzhiyun } 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun static inline void rockchip_dmcfreq_vop_bandwidth_update(struct dmcfreq_vop_info * vop_info)113*4882a593Smuzhiyunrockchip_dmcfreq_vop_bandwidth_update(struct dmcfreq_vop_info *vop_info) 114*4882a593Smuzhiyun { 115*4882a593Smuzhiyun } 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun static inline void rockchip_dmcfreq_vop_bandwidth_init(struct dmcfreq_common_info * info)118*4882a593Smuzhiyunrockchip_dmcfreq_vop_bandwidth_init(struct dmcfreq_common_info *info) 119*4882a593Smuzhiyun { 120*4882a593Smuzhiyun } 121*4882a593Smuzhiyun #endif 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif 124