1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Rockchip General Register Files definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2018, Collabora Ltd. 6*4882a593Smuzhiyun * Author: Enric Balletbo i Serra <enric.balletbo@collabora.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __SOC_RK3399_GRF_H 10*4882a593Smuzhiyun #define __SOC_RK3399_GRF_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* PMU GRF Registers */ 13*4882a593Smuzhiyun #define RK3399_PMUGRF_OS_REG2 0x308 14*4882a593Smuzhiyun #define RK3399_PMUGRF_DDRTYPE_SHIFT 13 15*4882a593Smuzhiyun #define RK3399_PMUGRF_DDRTYPE_MASK 7 16*4882a593Smuzhiyun #define RK3399_PMUGRF_DDRTYPE_DDR3 3 17*4882a593Smuzhiyun #define RK3399_PMUGRF_DDRTYPE_LPDDR2 5 18*4882a593Smuzhiyun #define RK3399_PMUGRF_DDRTYPE_LPDDR3 6 19*4882a593Smuzhiyun #define RK3399_PMUGRF_DDRTYPE_LPDDR4 7 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #endif 22