1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun * OpenIB.org BSD license below:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun * without modification, are permitted provided that the following
12*4882a593Smuzhiyun * conditions are met:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * - Redistributions of source code must retain the above
15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun * disclaimer.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun * provided with the distribution.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun * SOFTWARE.
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #ifndef SOC_NPS_MTM_H
34*4882a593Smuzhiyun #define SOC_NPS_MTM_H
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF
37*4882a593Smuzhiyun #define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3
38*4882a593Smuzhiyun
hw_schd_save(unsigned int * flags)39*4882a593Smuzhiyun static inline void hw_schd_save(unsigned int *flags)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun __asm__ __volatile__(
42*4882a593Smuzhiyun " .word %1\n"
43*4882a593Smuzhiyun " st r3,[%0]\n"
44*4882a593Smuzhiyun :
45*4882a593Smuzhiyun : "r"(flags), "i"(CTOP_INST_HWSCHD_OFF_R3)
46*4882a593Smuzhiyun : "r3", "memory");
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
hw_schd_restore(unsigned int flags)49*4882a593Smuzhiyun static inline void hw_schd_restore(unsigned int flags)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun __asm__ __volatile__(
52*4882a593Smuzhiyun " mov r3, %0\n"
53*4882a593Smuzhiyun " .word %1\n"
54*4882a593Smuzhiyun :
55*4882a593Smuzhiyun : "r"(flags), "i"(CTOP_INST_HWSCHD_RESTORE_R3)
56*4882a593Smuzhiyun : "r3");
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #endif /* SOC_NPS_MTM_H */
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