xref: /OK3568_Linux_fs/kernel/include/soc/mscc/ocelot_sys.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Microsemi Ocelot Switch driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2017 Microsemi Corporation
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef _MSCC_OCELOT_SYS_H_
9*4882a593Smuzhiyun #define _MSCC_OCELOT_SYS_H_
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define SYS_COUNT_RX_OCTETS_RSZ                           0x4
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define SYS_COUNT_TX_OCTETS_RSZ                           0x4
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define SYS_FRONT_PORT_MODE_RSZ                           0x4
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define SYS_FRONT_PORT_MODE_HDX_MODE                      BIT(0)
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #define SYS_FRM_AGING_AGE_TX_ENA                          BIT(20)
20*4882a593Smuzhiyun #define SYS_FRM_AGING_MAX_AGE(x)                          ((x) & GENMASK(19, 0))
21*4882a593Smuzhiyun #define SYS_FRM_AGING_MAX_AGE_M                           GENMASK(19, 0)
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x)                   (((x) << 10) & GENMASK(16, 10))
24*4882a593Smuzhiyun #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M                    GENMASK(16, 10)
25*4882a593Smuzhiyun #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x)                 (((x) & GENMASK(16, 10)) >> 10)
26*4882a593Smuzhiyun #define SYS_STAT_CFG_STAT_VIEW(x)                         ((x) & GENMASK(9, 0))
27*4882a593Smuzhiyun #define SYS_STAT_CFG_STAT_VIEW_M                          GENMASK(9, 0)
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define SYS_SW_STATUS_RSZ                                 0x4
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define SYS_SW_STATUS_PORT_RX_PAUSED                      BIT(0)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define SYS_MISC_CFG_PTP_RSRV_CLR                         BIT(1)
34*4882a593Smuzhiyun #define SYS_MISC_CFG_PTP_DIS_NEG_RO                       BIT(0)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define SYS_REW_MAC_HIGH_CFG_RSZ                          0x4
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define SYS_REW_MAC_LOW_CFG_RSZ                           0x4
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x)              (((x) << 6) & GENMASK(21, 6))
41*4882a593Smuzhiyun #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M               GENMASK(21, 6)
42*4882a593Smuzhiyun #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x)            (((x) & GENMASK(21, 6)) >> 6)
43*4882a593Smuzhiyun #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x)          ((x) & GENMASK(5, 0))
44*4882a593Smuzhiyun #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M           GENMASK(5, 0)
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x)              (((x) << 9) & GENMASK(17, 9))
47*4882a593Smuzhiyun #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M               GENMASK(17, 9)
48*4882a593Smuzhiyun #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x)            (((x) & GENMASK(17, 9)) >> 9)
49*4882a593Smuzhiyun #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x)               ((x) & GENMASK(8, 0))
50*4882a593Smuzhiyun #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M                GENMASK(8, 0)
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define SYS_ATOP_RSZ                                      0x4
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_RSZ                                0x4
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_FC_LINK_SPEED(x)                   (((x) << 26) & GENMASK(27, 26))
57*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_FC_LINK_SPEED_M                    GENMASK(27, 26)
58*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x)                 (((x) & GENMASK(27, 26)) >> 26)
59*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x)                  (((x) << 20) & GENMASK(25, 20))
60*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M                   GENMASK(25, 20)
61*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x)                (((x) & GENMASK(25, 20)) >> 20)
62*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA                     BIT(18)
63*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_TX_FC_ENA                          BIT(17)
64*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_RX_FC_ENA                          BIT(16)
65*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x)                   ((x) & GENMASK(15, 0))
66*4882a593Smuzhiyun #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M                    GENMASK(15, 0)
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun #define SYS_MMGT_RELCNT(x)                                (((x) << 16) & GENMASK(31, 16))
69*4882a593Smuzhiyun #define SYS_MMGT_RELCNT_M                                 GENMASK(31, 16)
70*4882a593Smuzhiyun #define SYS_MMGT_RELCNT_X(x)                              (((x) & GENMASK(31, 16)) >> 16)
71*4882a593Smuzhiyun #define SYS_MMGT_FREECNT(x)                               ((x) & GENMASK(15, 0))
72*4882a593Smuzhiyun #define SYS_MMGT_FREECNT_M                                GENMASK(15, 0)
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define SYS_MMGT_FAST_FREEVLD(x)                          (((x) << 4) & GENMASK(7, 4))
75*4882a593Smuzhiyun #define SYS_MMGT_FAST_FREEVLD_M                           GENMASK(7, 4)
76*4882a593Smuzhiyun #define SYS_MMGT_FAST_FREEVLD_X(x)                        (((x) & GENMASK(7, 4)) >> 4)
77*4882a593Smuzhiyun #define SYS_MMGT_FAST_RELVLD(x)                           ((x) & GENMASK(3, 0))
78*4882a593Smuzhiyun #define SYS_MMGT_FAST_RELVLD_M                            GENMASK(3, 0)
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun #define SYS_EVENTS_DIF_RSZ                                0x4
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define SYS_EVENTS_DIF_EV_DRX(x)                          (((x) << 6) & GENMASK(8, 6))
83*4882a593Smuzhiyun #define SYS_EVENTS_DIF_EV_DRX_M                           GENMASK(8, 6)
84*4882a593Smuzhiyun #define SYS_EVENTS_DIF_EV_DRX_X(x)                        (((x) & GENMASK(8, 6)) >> 6)
85*4882a593Smuzhiyun #define SYS_EVENTS_DIF_EV_DTX(x)                          ((x) & GENMASK(5, 0))
86*4882a593Smuzhiyun #define SYS_EVENTS_DIF_EV_DTX_M                           GENMASK(5, 0)
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun #define SYS_EVENTS_CORE_EV_FWR                            BIT(2)
89*4882a593Smuzhiyun #define SYS_EVENTS_CORE_EV_ANA(x)                         ((x) & GENMASK(1, 0))
90*4882a593Smuzhiyun #define SYS_EVENTS_CORE_EV_ANA_M                          GENMASK(1, 0)
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define SYS_CNT_GSZ                                       0x4
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #define SYS_PTP_STATUS_PTP_TXSTAMP_OAM                    BIT(29)
95*4882a593Smuzhiyun #define SYS_PTP_STATUS_PTP_OVFL                           BIT(28)
96*4882a593Smuzhiyun #define SYS_PTP_STATUS_PTP_MESS_VLD                       BIT(27)
97*4882a593Smuzhiyun #define SYS_PTP_STATUS_PTP_MESS_ID(x)                     (((x) << 21) & GENMASK(26, 21))
98*4882a593Smuzhiyun #define SYS_PTP_STATUS_PTP_MESS_ID_M                      GENMASK(26, 21)
99*4882a593Smuzhiyun #define SYS_PTP_STATUS_PTP_MESS_ID_X(x)                   (((x) & GENMASK(26, 21)) >> 21)
100*4882a593Smuzhiyun #define SYS_PTP_STATUS_PTP_MESS_TXPORT(x)                 (((x) << 16) & GENMASK(20, 16))
101*4882a593Smuzhiyun #define SYS_PTP_STATUS_PTP_MESS_TXPORT_M                  GENMASK(20, 16)
102*4882a593Smuzhiyun #define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x)               (((x) & GENMASK(20, 16)) >> 16)
103*4882a593Smuzhiyun #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x)                 ((x) & GENMASK(15, 0))
104*4882a593Smuzhiyun #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M                  GENMASK(15, 0)
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun #define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x)                    ((x) & GENMASK(29, 0))
107*4882a593Smuzhiyun #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M                     GENMASK(29, 0)
108*4882a593Smuzhiyun #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC                   BIT(31)
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define SYS_PTP_NXT_PTP_NXT                               BIT(0)
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun #define SYS_PTP_CFG_PTP_STAMP_WID(x)                      (((x) << 2) & GENMASK(7, 2))
113*4882a593Smuzhiyun #define SYS_PTP_CFG_PTP_STAMP_WID_M                       GENMASK(7, 2)
114*4882a593Smuzhiyun #define SYS_PTP_CFG_PTP_STAMP_WID_X(x)                    (((x) & GENMASK(7, 2)) >> 2)
115*4882a593Smuzhiyun #define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x)                   ((x) & GENMASK(1, 0))
116*4882a593Smuzhiyun #define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M                    GENMASK(1, 0)
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun #define SYS_RAM_INIT_RAM_INIT                             BIT(1)
119*4882a593Smuzhiyun #define SYS_RAM_INIT_RAM_CFG_HOOK                         BIT(0)
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun #endif
122