1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2015 Linaro Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __SOC_IMX_REVISION_H__ 7*4882a593Smuzhiyun #define __SOC_IMX_REVISION_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define IMX_CHIP_REVISION_1_0 0x10 10*4882a593Smuzhiyun #define IMX_CHIP_REVISION_1_1 0x11 11*4882a593Smuzhiyun #define IMX_CHIP_REVISION_1_2 0x12 12*4882a593Smuzhiyun #define IMX_CHIP_REVISION_1_3 0x13 13*4882a593Smuzhiyun #define IMX_CHIP_REVISION_1_4 0x14 14*4882a593Smuzhiyun #define IMX_CHIP_REVISION_1_5 0x15 15*4882a593Smuzhiyun #define IMX_CHIP_REVISION_2_0 0x20 16*4882a593Smuzhiyun #define IMX_CHIP_REVISION_2_1 0x21 17*4882a593Smuzhiyun #define IMX_CHIP_REVISION_2_2 0x22 18*4882a593Smuzhiyun #define IMX_CHIP_REVISION_2_3 0x23 19*4882a593Smuzhiyun #define IMX_CHIP_REVISION_3_0 0x30 20*4882a593Smuzhiyun #define IMX_CHIP_REVISION_3_1 0x31 21*4882a593Smuzhiyun #define IMX_CHIP_REVISION_3_2 0x32 22*4882a593Smuzhiyun #define IMX_CHIP_REVISION_3_3 0x33 23*4882a593Smuzhiyun #define IMX_CHIP_REVISION_UNKNOWN 0xff 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun int mx27_revision(void); 26*4882a593Smuzhiyun int mx31_revision(void); 27*4882a593Smuzhiyun int mx35_revision(void); 28*4882a593Smuzhiyun int mx51_revision(void); 29*4882a593Smuzhiyun int mx53_revision(void); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun unsigned int imx_get_soc_revision(void); 32*4882a593Smuzhiyun void imx_print_silicon_rev(const char *cpu, int srev); 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* __SOC_IMX_REVISION_H__ */ 35