xref: /OK3568_Linux_fs/kernel/include/soc/fsl/qe/ucc_fast.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Internal header file for UCC FAST unit routines.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Authors: 	Shlomi Gridish <gridish@freescale.com>
8*4882a593Smuzhiyun  * 		Li Yang <leoli@freescale.com>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun #ifndef __UCC_FAST_H__
11*4882a593Smuzhiyun #define __UCC_FAST_H__
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <soc/fsl/qe/immap_qe.h>
16*4882a593Smuzhiyun #include <soc/fsl/qe/qe.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <soc/fsl/qe/ucc.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /* Receive BD's status and length*/
21*4882a593Smuzhiyun #define R_E	0x80000000	/* buffer empty */
22*4882a593Smuzhiyun #define R_W	0x20000000	/* wrap bit */
23*4882a593Smuzhiyun #define R_I	0x10000000	/* interrupt on reception */
24*4882a593Smuzhiyun #define R_L	0x08000000	/* last */
25*4882a593Smuzhiyun #define R_F	0x04000000	/* first */
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* transmit BD's status and length*/
28*4882a593Smuzhiyun #define T_R	0x80000000	/* ready bit */
29*4882a593Smuzhiyun #define T_W	0x20000000	/* wrap bit */
30*4882a593Smuzhiyun #define T_I	0x10000000	/* interrupt on completion */
31*4882a593Smuzhiyun #define T_L	0x08000000	/* last */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /* Receive BD's status */
34*4882a593Smuzhiyun #define R_E_S	0x8000	/* buffer empty */
35*4882a593Smuzhiyun #define R_W_S	0x2000	/* wrap bit */
36*4882a593Smuzhiyun #define R_I_S	0x1000	/* interrupt on reception */
37*4882a593Smuzhiyun #define R_L_S	0x0800	/* last */
38*4882a593Smuzhiyun #define R_F_S	0x0400	/* first */
39*4882a593Smuzhiyun #define R_CM_S	0x0200	/* continuous mode */
40*4882a593Smuzhiyun #define R_LG_S  0x0020  /* frame length */
41*4882a593Smuzhiyun #define R_NO_S  0x0010  /* nonoctet */
42*4882a593Smuzhiyun #define R_AB_S  0x0008  /* abort */
43*4882a593Smuzhiyun #define R_CR_S	0x0004	/* crc */
44*4882a593Smuzhiyun #define R_OV_S	0x0002	/* overrun */
45*4882a593Smuzhiyun #define R_CD_S  0x0001  /* carrier detect */
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* transmit BD's status */
48*4882a593Smuzhiyun #define T_R_S	0x8000	/* ready bit */
49*4882a593Smuzhiyun #define T_W_S	0x2000	/* wrap bit */
50*4882a593Smuzhiyun #define T_I_S	0x1000	/* interrupt on completion */
51*4882a593Smuzhiyun #define T_L_S	0x0800	/* last */
52*4882a593Smuzhiyun #define T_TC_S	0x0400	/* crc */
53*4882a593Smuzhiyun #define T_TM_S	0x0200	/* continuous mode */
54*4882a593Smuzhiyun #define T_UN_S  0x0002  /* hdlc underrun */
55*4882a593Smuzhiyun #define T_CT_S  0x0001  /* hdlc carrier lost */
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun /* Rx Data buffer must be 4 bytes aligned in most cases */
58*4882a593Smuzhiyun #define UCC_FAST_RX_ALIGN			4
59*4882a593Smuzhiyun #define UCC_FAST_MRBLR_ALIGNMENT		4
60*4882a593Smuzhiyun #define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT	8
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun /* Sizes */
63*4882a593Smuzhiyun #define UCC_FAST_URFS_MIN_VAL				0x88
64*4882a593Smuzhiyun #define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR	8
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /* ucc_fast_channel_protocol_mode - UCC FAST mode */
67*4882a593Smuzhiyun enum ucc_fast_channel_protocol_mode {
68*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000,
69*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001,
70*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002,
71*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003,
72*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004,
73*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005,
74*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006,
75*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007,
76*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008,
77*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009,
78*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A,
79*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B,
80*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C,
81*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D,
82*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E,
83*4882a593Smuzhiyun 	UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */
87*4882a593Smuzhiyun enum ucc_fast_transparent_txrx {
88*4882a593Smuzhiyun 	UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000,
89*4882a593Smuzhiyun 	UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun /* UCC fast diagnostic mode */
93*4882a593Smuzhiyun enum ucc_fast_diag_mode {
94*4882a593Smuzhiyun 	UCC_FAST_DIAGNOSTIC_NORMAL = 0x0,
95*4882a593Smuzhiyun 	UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000,
96*4882a593Smuzhiyun 	UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000,
97*4882a593Smuzhiyun 	UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun /* UCC fast Sync length (transparent mode only) */
101*4882a593Smuzhiyun enum ucc_fast_sync_len {
102*4882a593Smuzhiyun 	UCC_FAST_SYNC_LEN_NOT_USED = 0x0,
103*4882a593Smuzhiyun 	UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000,
104*4882a593Smuzhiyun 	UCC_FAST_SYNC_LEN_8_BIT = 0x00008000,
105*4882a593Smuzhiyun 	UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun /* UCC fast RTS mode */
109*4882a593Smuzhiyun enum ucc_fast_ready_to_send {
110*4882a593Smuzhiyun 	UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000,
111*4882a593Smuzhiyun 	UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun /* UCC fast receiver decoding mode */
115*4882a593Smuzhiyun enum ucc_fast_rx_decoding_method {
116*4882a593Smuzhiyun 	UCC_FAST_RX_ENCODING_NRZ = 0x00000000,
117*4882a593Smuzhiyun 	UCC_FAST_RX_ENCODING_NRZI = 0x00000800,
118*4882a593Smuzhiyun 	UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000,
119*4882a593Smuzhiyun 	UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /* UCC fast transmitter encoding mode */
123*4882a593Smuzhiyun enum ucc_fast_tx_encoding_method {
124*4882a593Smuzhiyun 	UCC_FAST_TX_ENCODING_NRZ = 0x00000000,
125*4882a593Smuzhiyun 	UCC_FAST_TX_ENCODING_NRZI = 0x00000100,
126*4882a593Smuzhiyun 	UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200,
127*4882a593Smuzhiyun 	UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun /* UCC fast CRC length */
131*4882a593Smuzhiyun enum ucc_fast_transparent_tcrc {
132*4882a593Smuzhiyun 	UCC_FAST_16_BIT_CRC = 0x00000000,
133*4882a593Smuzhiyun 	UCC_FAST_CRC_RESERVED0 = 0x00000040,
134*4882a593Smuzhiyun 	UCC_FAST_32_BIT_CRC = 0x00000080,
135*4882a593Smuzhiyun 	UCC_FAST_CRC_RESERVED1 = 0x000000C0
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun /* Fast UCC initialization structure */
139*4882a593Smuzhiyun struct ucc_fast_info {
140*4882a593Smuzhiyun 	int ucc_num;
141*4882a593Smuzhiyun 	int tdm_num;
142*4882a593Smuzhiyun 	enum qe_clock rx_clock;
143*4882a593Smuzhiyun 	enum qe_clock tx_clock;
144*4882a593Smuzhiyun 	enum qe_clock rx_sync;
145*4882a593Smuzhiyun 	enum qe_clock tx_sync;
146*4882a593Smuzhiyun 	resource_size_t regs;
147*4882a593Smuzhiyun 	int irq;
148*4882a593Smuzhiyun 	u32 uccm_mask;
149*4882a593Smuzhiyun 	int bd_mem_part;
150*4882a593Smuzhiyun 	int brkpt_support;
151*4882a593Smuzhiyun 	int grant_support;
152*4882a593Smuzhiyun 	int tsa;
153*4882a593Smuzhiyun 	int cdp;
154*4882a593Smuzhiyun 	int cds;
155*4882a593Smuzhiyun 	int ctsp;
156*4882a593Smuzhiyun 	int ctss;
157*4882a593Smuzhiyun 	int tci;
158*4882a593Smuzhiyun 	int txsy;
159*4882a593Smuzhiyun 	int rtsm;
160*4882a593Smuzhiyun 	int revd;
161*4882a593Smuzhiyun 	int rsyn;
162*4882a593Smuzhiyun 	u16 max_rx_buf_length;
163*4882a593Smuzhiyun 	u16 urfs;
164*4882a593Smuzhiyun 	u16 urfet;
165*4882a593Smuzhiyun 	u16 urfset;
166*4882a593Smuzhiyun 	u16 utfs;
167*4882a593Smuzhiyun 	u16 utfet;
168*4882a593Smuzhiyun 	u16 utftt;
169*4882a593Smuzhiyun 	u16 ufpt;
170*4882a593Smuzhiyun 	enum ucc_fast_channel_protocol_mode mode;
171*4882a593Smuzhiyun 	enum ucc_fast_transparent_txrx ttx_trx;
172*4882a593Smuzhiyun 	enum ucc_fast_tx_encoding_method tenc;
173*4882a593Smuzhiyun 	enum ucc_fast_rx_decoding_method renc;
174*4882a593Smuzhiyun 	enum ucc_fast_transparent_tcrc tcrc;
175*4882a593Smuzhiyun 	enum ucc_fast_sync_len synl;
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun struct ucc_fast_private {
179*4882a593Smuzhiyun 	struct ucc_fast_info *uf_info;
180*4882a593Smuzhiyun 	struct ucc_fast __iomem *uf_regs; /* a pointer to the UCC regs. */
181*4882a593Smuzhiyun 	__be32 __iomem *p_ucce;	/* a pointer to the event register in memory. */
182*4882a593Smuzhiyun 	__be32 __iomem *p_uccm;	/* a pointer to the mask register in memory. */
183*4882a593Smuzhiyun #ifdef CONFIG_UGETH_TX_ON_DEMAND
184*4882a593Smuzhiyun 	__be16 __iomem *p_utodr;/* pointer to the transmit on demand register */
185*4882a593Smuzhiyun #endif
186*4882a593Smuzhiyun 	int enabled_tx;		/* Whether channel is enabled for Tx (ENT) */
187*4882a593Smuzhiyun 	int enabled_rx;		/* Whether channel is enabled for Rx (ENR) */
188*4882a593Smuzhiyun 	int stopped_tx;		/* Whether channel has been stopped for Tx
189*4882a593Smuzhiyun 				   (STOP_TX, etc.) */
190*4882a593Smuzhiyun 	int stopped_rx;		/* Whether channel has been stopped for Rx */
191*4882a593Smuzhiyun 	s32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx
192*4882a593Smuzhiyun 						    virtual fifo */
193*4882a593Smuzhiyun 	s32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx
194*4882a593Smuzhiyun 						    virtual fifo */
195*4882a593Smuzhiyun #ifdef STATISTICS
196*4882a593Smuzhiyun 	u32 tx_frames;		/* Transmitted frames counter. */
197*4882a593Smuzhiyun 	u32 rx_frames;		/* Received frames counter (only frames
198*4882a593Smuzhiyun 				   passed to application). */
199*4882a593Smuzhiyun 	u32 tx_discarded;	/* Discarded tx frames counter (frames that
200*4882a593Smuzhiyun 				   were discarded by the driver due to errors).
201*4882a593Smuzhiyun 				   */
202*4882a593Smuzhiyun 	u32 rx_discarded;	/* Discarded rx frames counter (frames that
203*4882a593Smuzhiyun 				   were discarded by the driver due to errors).
204*4882a593Smuzhiyun 				   */
205*4882a593Smuzhiyun #endif				/* STATISTICS */
206*4882a593Smuzhiyun 	u16 mrblr;		/* maximum receive buffer length */
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun /* ucc_fast_init
210*4882a593Smuzhiyun  * Initializes Fast UCC according to user provided parameters.
211*4882a593Smuzhiyun  *
212*4882a593Smuzhiyun  * uf_info  - (In) pointer to the fast UCC info structure.
213*4882a593Smuzhiyun  * uccf_ret - (Out) pointer to the fast UCC structure.
214*4882a593Smuzhiyun  */
215*4882a593Smuzhiyun int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun /* ucc_fast_free
218*4882a593Smuzhiyun  * Frees all resources for fast UCC.
219*4882a593Smuzhiyun  *
220*4882a593Smuzhiyun  * uccf - (In) pointer to the fast UCC structure.
221*4882a593Smuzhiyun  */
222*4882a593Smuzhiyun void ucc_fast_free(struct ucc_fast_private * uccf);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun /* ucc_fast_enable
225*4882a593Smuzhiyun  * Enables a fast UCC port.
226*4882a593Smuzhiyun  * This routine enables Tx and/or Rx through the General UCC Mode Register.
227*4882a593Smuzhiyun  *
228*4882a593Smuzhiyun  * uccf - (In) pointer to the fast UCC structure.
229*4882a593Smuzhiyun  * mode - (In) TX, RX, or both.
230*4882a593Smuzhiyun  */
231*4882a593Smuzhiyun void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun /* ucc_fast_disable
234*4882a593Smuzhiyun  * Disables a fast UCC port.
235*4882a593Smuzhiyun  * This routine disables Tx and/or Rx through the General UCC Mode Register.
236*4882a593Smuzhiyun  *
237*4882a593Smuzhiyun  * uccf - (In) pointer to the fast UCC structure.
238*4882a593Smuzhiyun  * mode - (In) TX, RX, or both.
239*4882a593Smuzhiyun  */
240*4882a593Smuzhiyun void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode);
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun /* ucc_fast_irq
243*4882a593Smuzhiyun  * Handles interrupts on fast UCC.
244*4882a593Smuzhiyun  * Called from the general interrupt routine to handle interrupts on fast UCC.
245*4882a593Smuzhiyun  *
246*4882a593Smuzhiyun  * uccf - (In) pointer to the fast UCC structure.
247*4882a593Smuzhiyun  */
248*4882a593Smuzhiyun void ucc_fast_irq(struct ucc_fast_private * uccf);
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun /* ucc_fast_transmit_on_demand
251*4882a593Smuzhiyun  * Immediately forces a poll of the transmitter for data to be sent.
252*4882a593Smuzhiyun  * Typically, the hardware performs a periodic poll for data that the
253*4882a593Smuzhiyun  * transmit routine has set up to be transmitted. In cases where
254*4882a593Smuzhiyun  * this polling cycle is not soon enough, this optional routine can
255*4882a593Smuzhiyun  * be invoked to force a poll right away, instead. Proper use for
256*4882a593Smuzhiyun  * each transmission for which this functionality is desired is to
257*4882a593Smuzhiyun  * call the transmit routine and then this routine right after.
258*4882a593Smuzhiyun  *
259*4882a593Smuzhiyun  * uccf - (In) pointer to the fast UCC structure.
260*4882a593Smuzhiyun  */
261*4882a593Smuzhiyun void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf);
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun u32 ucc_fast_get_qe_cr_subblock(int uccf_num);
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun void ucc_fast_dump_regs(struct ucc_fast_private * uccf);
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun #endif				/* __UCC_FAST_H__ */
268