1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Authors: Shlomi Gridish <gridish@freescale.com>
6*4882a593Smuzhiyun * Li Yang <leoli@freescale.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Description:
9*4882a593Smuzhiyun * Internal header file for UCC unit routines.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun #ifndef __UCC_H__
12*4882a593Smuzhiyun #define __UCC_H__
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <soc/fsl/qe/immap_qe.h>
15*4882a593Smuzhiyun #include <soc/fsl/qe/qe.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define STATISTICS
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define UCC_MAX_NUM 8
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Slow or fast type for UCCs.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun enum ucc_speed_type {
24*4882a593Smuzhiyun UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX,
25*4882a593Smuzhiyun UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* ucc_set_type
29*4882a593Smuzhiyun * Sets UCC to slow or fast mode.
30*4882a593Smuzhiyun *
31*4882a593Smuzhiyun * ucc_num - (In) number of UCC (0-7).
32*4882a593Smuzhiyun * speed - (In) slow or fast mode for UCC.
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
39*4882a593Smuzhiyun enum comm_dir mode);
40*4882a593Smuzhiyun int ucc_set_tdm_rxtx_clk(unsigned int tdm_num, enum qe_clock clock,
41*4882a593Smuzhiyun enum comm_dir mode);
42*4882a593Smuzhiyun int ucc_set_tdm_rxtx_sync(unsigned int tdm_num, enum qe_clock clock,
43*4882a593Smuzhiyun enum comm_dir mode);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* QE MUX clock routing for UCC
48*4882a593Smuzhiyun */
ucc_set_qe_mux_grant(unsigned int ucc_num,int set)49*4882a593Smuzhiyun static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
ucc_set_qe_mux_tsa(unsigned int ucc_num,int set)54*4882a593Smuzhiyun static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
ucc_set_qe_mux_bkpt(unsigned int ucc_num,int set)59*4882a593Smuzhiyun static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #endif /* __UCC_H__ */
65