1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Internal header file for QE TDM mode routines. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. All rights reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Authors: Zhao Qiang <qiang.zhao@nxp.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _QE_TDM_H_ 11*4882a593Smuzhiyun #define _QE_TDM_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/kernel.h> 14*4882a593Smuzhiyun #include <linux/list.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #include <soc/fsl/qe/immap_qe.h> 17*4882a593Smuzhiyun #include <soc/fsl/qe/qe.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include <soc/fsl/qe/ucc.h> 20*4882a593Smuzhiyun #include <soc/fsl/qe/ucc_fast.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* SI RAM entries */ 23*4882a593Smuzhiyun #define SIR_LAST 0x0001 24*4882a593Smuzhiyun #define SIR_BYTE 0x0002 25*4882a593Smuzhiyun #define SIR_CNT(x) ((x) << 2) 26*4882a593Smuzhiyun #define SIR_CSEL(x) ((x) << 5) 27*4882a593Smuzhiyun #define SIR_SGS 0x0200 28*4882a593Smuzhiyun #define SIR_SWTR 0x4000 29*4882a593Smuzhiyun #define SIR_MCC 0x8000 30*4882a593Smuzhiyun #define SIR_IDLE 0 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* SIxMR fields */ 33*4882a593Smuzhiyun #define SIMR_SAD(x) ((x) << 12) 34*4882a593Smuzhiyun #define SIMR_SDM_NORMAL 0x0000 35*4882a593Smuzhiyun #define SIMR_SDM_INTERNAL_LOOPBACK 0x0800 36*4882a593Smuzhiyun #define SIMR_SDM_MASK 0x0c00 37*4882a593Smuzhiyun #define SIMR_CRT 0x0040 38*4882a593Smuzhiyun #define SIMR_SL 0x0020 39*4882a593Smuzhiyun #define SIMR_CE 0x0010 40*4882a593Smuzhiyun #define SIMR_FE 0x0008 41*4882a593Smuzhiyun #define SIMR_GM 0x0004 42*4882a593Smuzhiyun #define SIMR_TFSD(n) (n) 43*4882a593Smuzhiyun #define SIMR_RFSD(n) ((n) << 8) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun enum tdm_ts_t { 46*4882a593Smuzhiyun TDM_TX_TS, 47*4882a593Smuzhiyun TDM_RX_TS 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun enum tdm_framer_t { 51*4882a593Smuzhiyun TDM_FRAMER_T1, 52*4882a593Smuzhiyun TDM_FRAMER_E1 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun enum tdm_mode_t { 56*4882a593Smuzhiyun TDM_INTERNAL_LOOPBACK, 57*4882a593Smuzhiyun TDM_NORMAL 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct si_mode_info { 61*4882a593Smuzhiyun u8 simr_rfsd; 62*4882a593Smuzhiyun u8 simr_tfsd; 63*4882a593Smuzhiyun u8 simr_crt; 64*4882a593Smuzhiyun u8 simr_sl; 65*4882a593Smuzhiyun u8 simr_ce; 66*4882a593Smuzhiyun u8 simr_fe; 67*4882a593Smuzhiyun u8 simr_gm; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct ucc_tdm_info { 71*4882a593Smuzhiyun struct ucc_fast_info uf_info; 72*4882a593Smuzhiyun struct si_mode_info si_info; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct ucc_tdm { 76*4882a593Smuzhiyun u16 tdm_port; /* port for this tdm:TDMA,TDMB */ 77*4882a593Smuzhiyun u32 siram_entry_id; 78*4882a593Smuzhiyun u16 __iomem *siram; 79*4882a593Smuzhiyun struct si1 __iomem *si_regs; 80*4882a593Smuzhiyun enum tdm_framer_t tdm_framer_type; 81*4882a593Smuzhiyun enum tdm_mode_t tdm_mode; 82*4882a593Smuzhiyun u8 num_of_ts; /* the number of timeslots in this tdm frame */ 83*4882a593Smuzhiyun u32 tx_ts_mask; /* tx time slot mask */ 84*4882a593Smuzhiyun u32 rx_ts_mask; /* rx time slot mask */ 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun int ucc_of_parse_tdm(struct device_node *np, struct ucc_tdm *utdm, 88*4882a593Smuzhiyun struct ucc_tdm_info *ut_info); 89*4882a593Smuzhiyun void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info); 90*4882a593Smuzhiyun #endif 91