1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Atmel SFR (Special Function Registers) register offsets and bit definitions. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Atmel 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Ludovic Desroches <ludovic.desroches@atmel.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _LINUX_MFD_SYSCON_ATMEL_SFR_H 11*4882a593Smuzhiyun #define _LINUX_MFD_SYSCON_ATMEL_SFR_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */ 14*4882a593Smuzhiyun #define AT91_SFR_CCFG_EBICSA 0x04 /* EBI Chip Select Register */ 15*4882a593Smuzhiyun /* 0x08 ~ 0x0c: Reserved */ 16*4882a593Smuzhiyun #define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */ 17*4882a593Smuzhiyun #define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */ 18*4882a593Smuzhiyun #define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */ 19*4882a593Smuzhiyun #define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */ 20*4882a593Smuzhiyun #define AT91_SFR_LS 0x7c /* Light Sleep Register */ 21*4882a593Smuzhiyun #define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */ 22*4882a593Smuzhiyun #define AT91_SFR_WPMR 0xe4 /* Write Protection Mode Register */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Field definitions */ 25*4882a593Smuzhiyun #define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs)) 26*4882a593Smuzhiyun #define AT91_SFR_CCFG_EBI_DBPUC BIT(8) 27*4882a593Smuzhiyun #define AT91_SFR_CCFG_EBI_DBPDC BIT(9) 28*4882a593Smuzhiyun #define AT91_SFR_CCFG_EBI_DRIVE BIT(17) 29*4882a593Smuzhiyun #define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24) 30*4882a593Smuzhiyun #define AT91_SFR_CCFG_DDR_MP_EN BIT(25) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define AT91_SFR_OHCIICR_RES(x) BIT(x) 33*4882a593Smuzhiyun #define AT91_SFR_OHCIICR_ARIE BIT(4) 34*4882a593Smuzhiyun #define AT91_SFR_OHCIICR_APPSTART BIT(5) 35*4882a593Smuzhiyun #define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x)) 36*4882a593Smuzhiyun #define AT91_SFR_OHCIICR_UDPPUDIS BIT(23) 37*4882a593Smuzhiyun #define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define AT91_SFR_OHCIISR_RIS(x) BIT(x) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define AT91_SFR_UTMISWAP_PORT(x) BIT(x) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define AT91_SFR_LS_VALUE(x) BIT(x) 46*4882a593Smuzhiyun #define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define AT91_SFR_WPMR_WPEN BIT(0) 49*4882a593Smuzhiyun #define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif /* _LINUX_MFD_SYSCON_ATMEL_SFR_H */ 52