1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Header file for the Atmel DDR/SDR SDRAM Controller 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 Atmel Corporation 6*4882a593Smuzhiyun * Nicolas Ferre <nicolas.ferre@atmel.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef AT91SAM9_DDRSDR_H 9*4882a593Smuzhiyun #define AT91SAM9_DDRSDR_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define AT91_DDRSDRC_MR 0x00 /* Mode Register */ 12*4882a593Smuzhiyun #define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */ 13*4882a593Smuzhiyun #define AT91_DDRSDRC_MODE_NORMAL 0 14*4882a593Smuzhiyun #define AT91_DDRSDRC_MODE_NOP 1 15*4882a593Smuzhiyun #define AT91_DDRSDRC_MODE_PRECHARGE 2 16*4882a593Smuzhiyun #define AT91_DDRSDRC_MODE_LMR 3 17*4882a593Smuzhiyun #define AT91_DDRSDRC_MODE_REFRESH 4 18*4882a593Smuzhiyun #define AT91_DDRSDRC_MODE_EXT_LMR 5 19*4882a593Smuzhiyun #define AT91_DDRSDRC_MODE_DEEP 6 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */ 22*4882a593Smuzhiyun #define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define AT91_DDRSDRC_CR 0x08 /* Configuration Register */ 25*4882a593Smuzhiyun #define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */ 26*4882a593Smuzhiyun #define AT91_DDRSDRC_NC_SDR8 (0 << 0) 27*4882a593Smuzhiyun #define AT91_DDRSDRC_NC_SDR9 (1 << 0) 28*4882a593Smuzhiyun #define AT91_DDRSDRC_NC_SDR10 (2 << 0) 29*4882a593Smuzhiyun #define AT91_DDRSDRC_NC_SDR11 (3 << 0) 30*4882a593Smuzhiyun #define AT91_DDRSDRC_NC_DDR9 (0 << 0) 31*4882a593Smuzhiyun #define AT91_DDRSDRC_NC_DDR10 (1 << 0) 32*4882a593Smuzhiyun #define AT91_DDRSDRC_NC_DDR11 (2 << 0) 33*4882a593Smuzhiyun #define AT91_DDRSDRC_NC_DDR12 (3 << 0) 34*4882a593Smuzhiyun #define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */ 35*4882a593Smuzhiyun #define AT91_DDRSDRC_NR_11 (0 << 2) 36*4882a593Smuzhiyun #define AT91_DDRSDRC_NR_12 (1 << 2) 37*4882a593Smuzhiyun #define AT91_DDRSDRC_NR_13 (2 << 2) 38*4882a593Smuzhiyun #define AT91_DDRSDRC_NR_14 (3 << 2) 39*4882a593Smuzhiyun #define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ 40*4882a593Smuzhiyun #define AT91_DDRSDRC_CAS_2 (2 << 4) 41*4882a593Smuzhiyun #define AT91_DDRSDRC_CAS_3 (3 << 4) 42*4882a593Smuzhiyun #define AT91_DDRSDRC_CAS_25 (6 << 4) 43*4882a593Smuzhiyun #define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */ 44*4882a593Smuzhiyun #define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */ 45*4882a593Smuzhiyun #define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */ 46*4882a593Smuzhiyun #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */ 47*4882a593Smuzhiyun #define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */ 48*4882a593Smuzhiyun #define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */ 51*4882a593Smuzhiyun #define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */ 52*4882a593Smuzhiyun #define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */ 53*4882a593Smuzhiyun #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */ 54*4882a593Smuzhiyun #define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */ 55*4882a593Smuzhiyun #define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */ 56*4882a593Smuzhiyun #define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */ 57*4882a593Smuzhiyun #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */ 58*4882a593Smuzhiyun #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */ 59*4882a593Smuzhiyun #define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */ 62*4882a593Smuzhiyun #define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */ 63*4882a593Smuzhiyun #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */ 64*4882a593Smuzhiyun #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */ 65*4882a593Smuzhiyun #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */ 68*4882a593Smuzhiyun #define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */ 69*4882a593Smuzhiyun #define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */ 70*4882a593Smuzhiyun #define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */ 71*4882a593Smuzhiyun #define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ 74*4882a593Smuzhiyun #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */ 75*4882a593Smuzhiyun #define AT91_DDRSDRC_LPCB_DISABLE 0 76*4882a593Smuzhiyun #define AT91_DDRSDRC_LPCB_SELF_REFRESH 1 77*4882a593Smuzhiyun #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 78*4882a593Smuzhiyun #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 79*4882a593Smuzhiyun #define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ 80*4882a593Smuzhiyun #define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */ 81*4882a593Smuzhiyun #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ 82*4882a593Smuzhiyun #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ 83*4882a593Smuzhiyun #define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ 84*4882a593Smuzhiyun #define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */ 85*4882a593Smuzhiyun #define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12) 86*4882a593Smuzhiyun #define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12) 87*4882a593Smuzhiyun #define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12) 88*4882a593Smuzhiyun #define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */ 89*4882a593Smuzhiyun #define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */ 92*4882a593Smuzhiyun #define AT91_DDRSDRC_MD (7 << 0) /* Memory Device Type */ 93*4882a593Smuzhiyun #define AT91_DDRSDRC_MD_SDR 0 94*4882a593Smuzhiyun #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 95*4882a593Smuzhiyun #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 96*4882a593Smuzhiyun #define AT91_DDRSDRC_MD_LPDDR3 5 97*4882a593Smuzhiyun #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ 98*4882a593Smuzhiyun #define AT91_DDRSDRC_MD_LPDDR2 7 99*4882a593Smuzhiyun #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ 100*4882a593Smuzhiyun #define AT91_DDRSDRC_DBW_32BITS (0 << 4) 101*4882a593Smuzhiyun #define AT91_DDRSDRC_DBW_16BITS (1 << 4) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */ 104*4882a593Smuzhiyun #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */ 105*4882a593Smuzhiyun #define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */ 106*4882a593Smuzhiyun #define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */ 107*4882a593Smuzhiyun #define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */ 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */ 110*4882a593Smuzhiyun #define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */ 115*4882a593Smuzhiyun #define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */ 116*4882a593Smuzhiyun #define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */ 117*4882a593Smuzhiyun #define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */ 120*4882a593Smuzhiyun #define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */ 121*4882a593Smuzhiyun #define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */ 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #endif 124