1*4882a593Smuzhiyun /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright(c) 2018 Intel Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef TID_RDMA_DEFS_H 8*4882a593Smuzhiyun #define TID_RDMA_DEFS_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <rdma/ib_pack.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct tid_rdma_read_req { 13*4882a593Smuzhiyun __le32 kdeth0; 14*4882a593Smuzhiyun __le32 kdeth1; 15*4882a593Smuzhiyun struct ib_reth reth; 16*4882a593Smuzhiyun __be32 tid_flow_psn; 17*4882a593Smuzhiyun __be32 tid_flow_qp; 18*4882a593Smuzhiyun __be32 verbs_qp; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct tid_rdma_read_resp { 22*4882a593Smuzhiyun __le32 kdeth0; 23*4882a593Smuzhiyun __le32 kdeth1; 24*4882a593Smuzhiyun __be32 aeth; 25*4882a593Smuzhiyun __be32 reserved[4]; 26*4882a593Smuzhiyun __be32 verbs_psn; 27*4882a593Smuzhiyun __be32 verbs_qp; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct tid_rdma_write_req { 31*4882a593Smuzhiyun __le32 kdeth0; 32*4882a593Smuzhiyun __le32 kdeth1; 33*4882a593Smuzhiyun struct ib_reth reth; 34*4882a593Smuzhiyun __be32 reserved[2]; 35*4882a593Smuzhiyun __be32 verbs_qp; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun struct tid_rdma_write_resp { 39*4882a593Smuzhiyun __le32 kdeth0; 40*4882a593Smuzhiyun __le32 kdeth1; 41*4882a593Smuzhiyun __be32 aeth; 42*4882a593Smuzhiyun __be32 reserved[3]; 43*4882a593Smuzhiyun __be32 tid_flow_psn; 44*4882a593Smuzhiyun __be32 tid_flow_qp; 45*4882a593Smuzhiyun __be32 verbs_qp; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct tid_rdma_write_data { 49*4882a593Smuzhiyun __le32 kdeth0; 50*4882a593Smuzhiyun __le32 kdeth1; 51*4882a593Smuzhiyun __be32 reserved[6]; 52*4882a593Smuzhiyun __be32 verbs_qp; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun struct tid_rdma_resync { 56*4882a593Smuzhiyun __le32 kdeth0; 57*4882a593Smuzhiyun __le32 kdeth1; 58*4882a593Smuzhiyun __be32 reserved[6]; 59*4882a593Smuzhiyun __be32 verbs_qp; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct tid_rdma_ack { 63*4882a593Smuzhiyun __le32 kdeth0; 64*4882a593Smuzhiyun __le32 kdeth1; 65*4882a593Smuzhiyun __be32 aeth; 66*4882a593Smuzhiyun __be32 reserved[2]; 67*4882a593Smuzhiyun __be32 tid_flow_psn; 68*4882a593Smuzhiyun __be32 verbs_psn; 69*4882a593Smuzhiyun __be32 tid_flow_qp; 70*4882a593Smuzhiyun __be32 verbs_qp; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * TID RDMA Opcodes 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #define IB_OPCODE_TID_RDMA 0xe0 77*4882a593Smuzhiyun enum { 78*4882a593Smuzhiyun IB_OPCODE_WRITE_REQ = 0x0, 79*4882a593Smuzhiyun IB_OPCODE_WRITE_RESP = 0x1, 80*4882a593Smuzhiyun IB_OPCODE_WRITE_DATA = 0x2, 81*4882a593Smuzhiyun IB_OPCODE_WRITE_DATA_LAST = 0x3, 82*4882a593Smuzhiyun IB_OPCODE_READ_REQ = 0x4, 83*4882a593Smuzhiyun IB_OPCODE_READ_RESP = 0x5, 84*4882a593Smuzhiyun IB_OPCODE_RESYNC = 0x6, 85*4882a593Smuzhiyun IB_OPCODE_ACK = 0x7, 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun IB_OPCODE(TID_RDMA, WRITE_REQ), 88*4882a593Smuzhiyun IB_OPCODE(TID_RDMA, WRITE_RESP), 89*4882a593Smuzhiyun IB_OPCODE(TID_RDMA, WRITE_DATA), 90*4882a593Smuzhiyun IB_OPCODE(TID_RDMA, WRITE_DATA_LAST), 91*4882a593Smuzhiyun IB_OPCODE(TID_RDMA, READ_REQ), 92*4882a593Smuzhiyun IB_OPCODE(TID_RDMA, READ_RESP), 93*4882a593Smuzhiyun IB_OPCODE(TID_RDMA, RESYNC), 94*4882a593Smuzhiyun IB_OPCODE(TID_RDMA, ACK), 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define TID_OP(x) IB_OPCODE_TID_RDMA_##x 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* 100*4882a593Smuzhiyun * Define TID RDMA specific WR opcodes. The ib_wr_opcode 101*4882a593Smuzhiyun * enum already provides some reserved values for use by 102*4882a593Smuzhiyun * low level drivers. Two of those are used but renamed 103*4882a593Smuzhiyun * to be more descriptive. 104*4882a593Smuzhiyun */ 105*4882a593Smuzhiyun #define IB_WR_TID_RDMA_WRITE IB_WR_RESERVED1 106*4882a593Smuzhiyun #define IB_WR_TID_RDMA_READ IB_WR_RESERVED2 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #endif /* TID_RDMA_DEFS_H */ 109