1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * cisreg.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * The initial developer of the original code is David A. Hinds 6*4882a593Smuzhiyun * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds 7*4882a593Smuzhiyun * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * (C) 1999 David A. Hinds 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _LINUX_CISREG_H 13*4882a593Smuzhiyun #define _LINUX_CISREG_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Offsets from ConfigBase for CIS registers 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define CISREG_COR 0x00 19*4882a593Smuzhiyun #define CISREG_CCSR 0x02 20*4882a593Smuzhiyun #define CISREG_PRR 0x04 21*4882a593Smuzhiyun #define CISREG_SCR 0x06 22*4882a593Smuzhiyun #define CISREG_ESR 0x08 23*4882a593Smuzhiyun #define CISREG_IOBASE_0 0x0a 24*4882a593Smuzhiyun #define CISREG_IOBASE_1 0x0c 25*4882a593Smuzhiyun #define CISREG_IOBASE_2 0x0e 26*4882a593Smuzhiyun #define CISREG_IOBASE_3 0x10 27*4882a593Smuzhiyun #define CISREG_IOSIZE 0x12 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Configuration Option Register 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun #define COR_CONFIG_MASK 0x3f 33*4882a593Smuzhiyun #define COR_MFC_CONFIG_MASK 0x38 34*4882a593Smuzhiyun #define COR_FUNC_ENA 0x01 35*4882a593Smuzhiyun #define COR_ADDR_DECODE 0x02 36*4882a593Smuzhiyun #define COR_IREQ_ENA 0x04 37*4882a593Smuzhiyun #define COR_LEVEL_REQ 0x40 38*4882a593Smuzhiyun #define COR_SOFT_RESET 0x80 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * Card Configuration and Status Register 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun #define CCSR_INTR_ACK 0x01 44*4882a593Smuzhiyun #define CCSR_INTR_PENDING 0x02 45*4882a593Smuzhiyun #define CCSR_POWER_DOWN 0x04 46*4882a593Smuzhiyun #define CCSR_AUDIO_ENA 0x08 47*4882a593Smuzhiyun #define CCSR_IOIS8 0x20 48*4882a593Smuzhiyun #define CCSR_SIGCHG_ENA 0x40 49*4882a593Smuzhiyun #define CCSR_CHANGED 0x80 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Pin Replacement Register 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun #define PRR_WP_STATUS 0x01 55*4882a593Smuzhiyun #define PRR_READY_STATUS 0x02 56*4882a593Smuzhiyun #define PRR_BVD2_STATUS 0x04 57*4882a593Smuzhiyun #define PRR_BVD1_STATUS 0x08 58*4882a593Smuzhiyun #define PRR_WP_EVENT 0x10 59*4882a593Smuzhiyun #define PRR_READY_EVENT 0x20 60*4882a593Smuzhiyun #define PRR_BVD2_EVENT 0x40 61*4882a593Smuzhiyun #define PRR_BVD1_EVENT 0x80 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * Socket and Copy Register 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun #define SCR_SOCKET_NUM 0x0f 67*4882a593Smuzhiyun #define SCR_COPY_NUM 0x70 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * Extended Status Register 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun #define ESR_REQ_ATTN_ENA 0x01 73*4882a593Smuzhiyun #define ESR_REQ_ATTN 0x10 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * CardBus Function Status Registers 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun #define CBFN_EVENT 0x00 79*4882a593Smuzhiyun #define CBFN_MASK 0x04 80*4882a593Smuzhiyun #define CBFN_STATE 0x08 81*4882a593Smuzhiyun #define CBFN_FORCE 0x0c 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* 84*4882a593Smuzhiyun * These apply to all the CardBus function registers 85*4882a593Smuzhiyun */ 86*4882a593Smuzhiyun #define CBFN_WP 0x0001 87*4882a593Smuzhiyun #define CBFN_READY 0x0002 88*4882a593Smuzhiyun #define CBFN_BVD2 0x0004 89*4882a593Smuzhiyun #define CBFN_BVD1 0x0008 90*4882a593Smuzhiyun #define CBFN_GWAKE 0x0010 91*4882a593Smuzhiyun #define CBFN_INTR 0x8000 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* 94*4882a593Smuzhiyun * Extra bits in the Function Event Mask Register 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun #define FEMR_BAM_ENA 0x0020 97*4882a593Smuzhiyun #define FEMR_PWM_ENA 0x0040 98*4882a593Smuzhiyun #define FEMR_WKUP_MASK 0x4000 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * Indirect Addressing Registers for Zoomed Video: these are addresses 102*4882a593Smuzhiyun * in common memory space 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun #define CISREG_ICTRL0 0x02 /* control registers */ 105*4882a593Smuzhiyun #define CISREG_ICTRL1 0x03 106*4882a593Smuzhiyun #define CISREG_IADDR0 0x04 /* address registers */ 107*4882a593Smuzhiyun #define CISREG_IADDR1 0x05 108*4882a593Smuzhiyun #define CISREG_IADDR2 0x06 109*4882a593Smuzhiyun #define CISREG_IADDR3 0x07 110*4882a593Smuzhiyun #define CISREG_IDATA0 0x08 /* data registers */ 111*4882a593Smuzhiyun #define CISREG_IDATA1 0x09 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define ICTRL0_COMMON 0x01 114*4882a593Smuzhiyun #define ICTRL0_AUTOINC 0x02 115*4882a593Smuzhiyun #define ICTRL0_BYTEGRAN 0x04 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #endif /* _LINUX_CISREG_H */ 118