xref: /OK3568_Linux_fs/kernel/include/net/caif/caif_hsi.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) ST-Ericsson AB 2010
4*4882a593Smuzhiyun  * Author:  Daniel Martensson / daniel.martensson@stericsson.com
5*4882a593Smuzhiyun  *	    Dmitry.Tarnyagin  / dmitry.tarnyagin@stericsson.com
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef CAIF_HSI_H_
9*4882a593Smuzhiyun #define CAIF_HSI_H_
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <net/caif/caif_layer.h>
12*4882a593Smuzhiyun #include <net/caif/caif_device.h>
13*4882a593Smuzhiyun #include <linux/atomic.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun  * Maximum number of CAIF frames that can reside in the same HSI frame.
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun #define CFHSI_MAX_PKTS 15
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun  * Maximum number of bytes used for the frame that can be embedded in the
22*4882a593Smuzhiyun  * HSI descriptor.
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun #define CFHSI_MAX_EMB_FRM_SZ 96
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun  * Decides if HSI buffers should be prefilled with 0xFF pattern for easier
28*4882a593Smuzhiyun  * debugging. Both TX and RX buffers will be filled before the transfer.
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun #define CFHSI_DBG_PREFILL		0
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /* Structure describing a HSI packet descriptor. */
33*4882a593Smuzhiyun #pragma pack(1) /* Byte alignment. */
34*4882a593Smuzhiyun struct cfhsi_desc {
35*4882a593Smuzhiyun 	u8 header;
36*4882a593Smuzhiyun 	u8 offset;
37*4882a593Smuzhiyun 	u16 cffrm_len[CFHSI_MAX_PKTS];
38*4882a593Smuzhiyun 	u8 emb_frm[CFHSI_MAX_EMB_FRM_SZ];
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun #pragma pack() /* Default alignment. */
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* Size of the complete HSI packet descriptor. */
43*4882a593Smuzhiyun #define CFHSI_DESC_SZ (sizeof(struct cfhsi_desc))
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun /*
46*4882a593Smuzhiyun  * Size of the complete HSI packet descriptor excluding the optional embedded
47*4882a593Smuzhiyun  * CAIF frame.
48*4882a593Smuzhiyun  */
49*4882a593Smuzhiyun #define CFHSI_DESC_SHORT_SZ (CFHSI_DESC_SZ - CFHSI_MAX_EMB_FRM_SZ)
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun  * Maximum bytes transferred in one transfer.
53*4882a593Smuzhiyun  */
54*4882a593Smuzhiyun #define CFHSI_MAX_CAIF_FRAME_SZ 4096
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun #define CFHSI_MAX_PAYLOAD_SZ (CFHSI_MAX_PKTS * CFHSI_MAX_CAIF_FRAME_SZ)
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun /* Size of the complete HSI TX buffer. */
59*4882a593Smuzhiyun #define CFHSI_BUF_SZ_TX (CFHSI_DESC_SZ + CFHSI_MAX_PAYLOAD_SZ)
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /* Size of the complete HSI RX buffer. */
62*4882a593Smuzhiyun #define CFHSI_BUF_SZ_RX ((2 * CFHSI_DESC_SZ) + CFHSI_MAX_PAYLOAD_SZ)
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun /* Bitmasks for the HSI descriptor. */
65*4882a593Smuzhiyun #define CFHSI_PIGGY_DESC		(0x01 << 7)
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define CFHSI_TX_STATE_IDLE			0
68*4882a593Smuzhiyun #define CFHSI_TX_STATE_XFER			1
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define CFHSI_RX_STATE_DESC			0
71*4882a593Smuzhiyun #define CFHSI_RX_STATE_PAYLOAD			1
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun /* Bitmasks for power management. */
74*4882a593Smuzhiyun #define CFHSI_WAKE_UP				0
75*4882a593Smuzhiyun #define CFHSI_WAKE_UP_ACK			1
76*4882a593Smuzhiyun #define CFHSI_WAKE_DOWN_ACK			2
77*4882a593Smuzhiyun #define CFHSI_AWAKE				3
78*4882a593Smuzhiyun #define CFHSI_WAKELOCK_HELD			4
79*4882a593Smuzhiyun #define CFHSI_SHUTDOWN				5
80*4882a593Smuzhiyun #define CFHSI_FLUSH_FIFO			6
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #ifndef CFHSI_INACTIVITY_TOUT
83*4882a593Smuzhiyun #define CFHSI_INACTIVITY_TOUT			(1 * HZ)
84*4882a593Smuzhiyun #endif /* CFHSI_INACTIVITY_TOUT */
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #ifndef CFHSI_WAKE_TOUT
87*4882a593Smuzhiyun #define CFHSI_WAKE_TOUT			(3 * HZ)
88*4882a593Smuzhiyun #endif /* CFHSI_WAKE_TOUT */
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #ifndef CFHSI_MAX_RX_RETRIES
91*4882a593Smuzhiyun #define CFHSI_MAX_RX_RETRIES		(10 * HZ)
92*4882a593Smuzhiyun #endif
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun /* Structure implemented by the CAIF HSI driver. */
95*4882a593Smuzhiyun struct cfhsi_cb_ops {
96*4882a593Smuzhiyun 	void (*tx_done_cb) (struct cfhsi_cb_ops *drv);
97*4882a593Smuzhiyun 	void (*rx_done_cb) (struct cfhsi_cb_ops *drv);
98*4882a593Smuzhiyun 	void (*wake_up_cb) (struct cfhsi_cb_ops *drv);
99*4882a593Smuzhiyun 	void (*wake_down_cb) (struct cfhsi_cb_ops *drv);
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun /* Structure implemented by HSI device. */
103*4882a593Smuzhiyun struct cfhsi_ops {
104*4882a593Smuzhiyun 	int (*cfhsi_up) (struct cfhsi_ops *dev);
105*4882a593Smuzhiyun 	int (*cfhsi_down) (struct cfhsi_ops *dev);
106*4882a593Smuzhiyun 	int (*cfhsi_tx) (u8 *ptr, int len, struct cfhsi_ops *dev);
107*4882a593Smuzhiyun 	int (*cfhsi_rx) (u8 *ptr, int len, struct cfhsi_ops *dev);
108*4882a593Smuzhiyun 	int (*cfhsi_wake_up) (struct cfhsi_ops *dev);
109*4882a593Smuzhiyun 	int (*cfhsi_wake_down) (struct cfhsi_ops *dev);
110*4882a593Smuzhiyun 	int (*cfhsi_get_peer_wake) (struct cfhsi_ops *dev, bool *status);
111*4882a593Smuzhiyun 	int (*cfhsi_fifo_occupancy) (struct cfhsi_ops *dev, size_t *occupancy);
112*4882a593Smuzhiyun 	int (*cfhsi_rx_cancel)(struct cfhsi_ops *dev);
113*4882a593Smuzhiyun 	struct cfhsi_cb_ops *cb_ops;
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun /* Structure holds status of received CAIF frames processing */
117*4882a593Smuzhiyun struct cfhsi_rx_state {
118*4882a593Smuzhiyun 	int state;
119*4882a593Smuzhiyun 	int nfrms;
120*4882a593Smuzhiyun 	int pld_len;
121*4882a593Smuzhiyun 	int retries;
122*4882a593Smuzhiyun 	bool piggy_desc;
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun /* Priority mapping */
126*4882a593Smuzhiyun enum {
127*4882a593Smuzhiyun 	CFHSI_PRIO_CTL = 0,
128*4882a593Smuzhiyun 	CFHSI_PRIO_VI,
129*4882a593Smuzhiyun 	CFHSI_PRIO_VO,
130*4882a593Smuzhiyun 	CFHSI_PRIO_BEBK,
131*4882a593Smuzhiyun 	CFHSI_PRIO_LAST,
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun struct cfhsi_config {
135*4882a593Smuzhiyun 	u32 inactivity_timeout;
136*4882a593Smuzhiyun 	u32 aggregation_timeout;
137*4882a593Smuzhiyun 	u32 head_align;
138*4882a593Smuzhiyun 	u32 tail_align;
139*4882a593Smuzhiyun 	u32 q_high_mark;
140*4882a593Smuzhiyun 	u32 q_low_mark;
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun /* Structure implemented by CAIF HSI drivers. */
144*4882a593Smuzhiyun struct cfhsi {
145*4882a593Smuzhiyun 	struct caif_dev_common cfdev;
146*4882a593Smuzhiyun 	struct net_device *ndev;
147*4882a593Smuzhiyun 	struct platform_device *pdev;
148*4882a593Smuzhiyun 	struct sk_buff_head qhead[CFHSI_PRIO_LAST];
149*4882a593Smuzhiyun 	struct cfhsi_cb_ops cb_ops;
150*4882a593Smuzhiyun 	struct cfhsi_ops *ops;
151*4882a593Smuzhiyun 	int tx_state;
152*4882a593Smuzhiyun 	struct cfhsi_rx_state rx_state;
153*4882a593Smuzhiyun 	struct cfhsi_config cfg;
154*4882a593Smuzhiyun 	int rx_len;
155*4882a593Smuzhiyun 	u8 *rx_ptr;
156*4882a593Smuzhiyun 	u8 *tx_buf;
157*4882a593Smuzhiyun 	u8 *rx_buf;
158*4882a593Smuzhiyun 	u8 *rx_flip_buf;
159*4882a593Smuzhiyun 	spinlock_t lock;
160*4882a593Smuzhiyun 	int flow_off_sent;
161*4882a593Smuzhiyun 	struct list_head list;
162*4882a593Smuzhiyun 	struct work_struct wake_up_work;
163*4882a593Smuzhiyun 	struct work_struct wake_down_work;
164*4882a593Smuzhiyun 	struct work_struct out_of_sync_work;
165*4882a593Smuzhiyun 	struct workqueue_struct *wq;
166*4882a593Smuzhiyun 	wait_queue_head_t wake_up_wait;
167*4882a593Smuzhiyun 	wait_queue_head_t wake_down_wait;
168*4882a593Smuzhiyun 	wait_queue_head_t flush_fifo_wait;
169*4882a593Smuzhiyun 	struct timer_list inactivity_timer;
170*4882a593Smuzhiyun 	struct timer_list rx_slowpath_timer;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	/* TX aggregation */
173*4882a593Smuzhiyun 	int aggregation_len;
174*4882a593Smuzhiyun 	struct timer_list aggregation_timer;
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 	unsigned long bits;
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun extern struct platform_driver cfhsi_driver;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun /**
181*4882a593Smuzhiyun  * enum ifla_caif_hsi - CAIF HSI NetlinkRT parameters.
182*4882a593Smuzhiyun  * @IFLA_CAIF_HSI_INACTIVITY_TOUT: Inactivity timeout before
183*4882a593Smuzhiyun  *			taking the HSI wakeline down, in milliseconds.
184*4882a593Smuzhiyun  * When using RT Netlink to create, destroy or configure a CAIF HSI interface,
185*4882a593Smuzhiyun  * enum ifla_caif_hsi is used to specify the configuration attributes.
186*4882a593Smuzhiyun  */
187*4882a593Smuzhiyun enum ifla_caif_hsi {
188*4882a593Smuzhiyun 	__IFLA_CAIF_HSI_UNSPEC,
189*4882a593Smuzhiyun 	__IFLA_CAIF_HSI_INACTIVITY_TOUT,
190*4882a593Smuzhiyun 	__IFLA_CAIF_HSI_AGGREGATION_TOUT,
191*4882a593Smuzhiyun 	__IFLA_CAIF_HSI_HEAD_ALIGN,
192*4882a593Smuzhiyun 	__IFLA_CAIF_HSI_TAIL_ALIGN,
193*4882a593Smuzhiyun 	__IFLA_CAIF_HSI_QHIGH_WATERMARK,
194*4882a593Smuzhiyun 	__IFLA_CAIF_HSI_QLOW_WATERMARK,
195*4882a593Smuzhiyun 	__IFLA_CAIF_HSI_MAX
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun struct cfhsi_ops *cfhsi_get_ops(void);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun #endif		/* CAIF_HSI_H_ */
201