1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* include/net/ax88796.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2005 Simtec Electronics 5*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __NET_AX88796_PLAT_H 9*4882a593Smuzhiyun #define __NET_AX88796_PLAT_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct sk_buff; 12*4882a593Smuzhiyun struct net_device; 13*4882a593Smuzhiyun struct platform_device; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define AXFLG_HAS_EEPROM (1<<0) 16*4882a593Smuzhiyun #define AXFLG_MAC_FROMDEV (1<<1) /* device already has MAC */ 17*4882a593Smuzhiyun #define AXFLG_HAS_93CX6 (1<<2) /* use eeprom_93cx6 driver */ 18*4882a593Smuzhiyun #define AXFLG_MAC_FROMPLATFORM (1<<3) /* MAC given by platform data */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct ax_plat_data { 21*4882a593Smuzhiyun unsigned int flags; 22*4882a593Smuzhiyun unsigned char wordlength; /* 1 or 2 */ 23*4882a593Smuzhiyun unsigned char dcr_val; /* default value for DCR */ 24*4882a593Smuzhiyun unsigned char rcr_val; /* default value for RCR */ 25*4882a593Smuzhiyun unsigned char gpoc_val; /* default value for GPOC */ 26*4882a593Smuzhiyun u32 *reg_offsets; /* register offsets */ 27*4882a593Smuzhiyun u8 *mac_addr; /* MAC addr (only used when 28*4882a593Smuzhiyun AXFLG_MAC_FROMPLATFORM is used */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* uses default ax88796 buffer if set to NULL */ 31*4882a593Smuzhiyun void (*block_output)(struct net_device *dev, int count, 32*4882a593Smuzhiyun const unsigned char *buf, int star_page); 33*4882a593Smuzhiyun void (*block_input)(struct net_device *dev, int count, 34*4882a593Smuzhiyun struct sk_buff *skb, int ring_offset); 35*4882a593Smuzhiyun /* returns nonzero if a pending interrupt request might by caused by 36*4882a593Smuzhiyun * the ax88786. Handles all interrupts if set to NULL 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun int (*check_irq)(struct platform_device *pdev); 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* __NET_AX88796_PLAT_H */ 42