1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2017 IBM Corp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _MISC_CXLLIB_H 7*4882a593Smuzhiyun #define _MISC_CXLLIB_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/pci.h> 10*4882a593Smuzhiyun #include <asm/reg.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * cxl driver exports a in-kernel 'library' API which can be called by 14*4882a593Smuzhiyun * other drivers to help interacting with an IBM XSL. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * tells whether capi is supported on the PCIe slot where the 19*4882a593Smuzhiyun * device is seated 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * Input: 22*4882a593Smuzhiyun * dev: device whose slot needs to be checked 23*4882a593Smuzhiyun * flags: 0 for the time being 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * Returns the configuration parameters to be used by the XSL or device 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * Input: 32*4882a593Smuzhiyun * dev: device, used to find PHB 33*4882a593Smuzhiyun * Output: 34*4882a593Smuzhiyun * struct cxllib_xsl_config: 35*4882a593Smuzhiyun * version 36*4882a593Smuzhiyun * capi BAR address, i.e. 0x2000000000000-0x2FFFFFFFFFFFF 37*4882a593Smuzhiyun * capi BAR size 38*4882a593Smuzhiyun * data send control (XSL_DSNCTL) 39*4882a593Smuzhiyun * dummy read address (XSL_DRA) 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define CXL_XSL_CONFIG_VERSION1 1 42*4882a593Smuzhiyun struct cxllib_xsl_config { 43*4882a593Smuzhiyun u32 version; /* format version for register encoding */ 44*4882a593Smuzhiyun u32 log_bar_size;/* log size of the capi_window */ 45*4882a593Smuzhiyun u64 bar_addr; /* address of the start of capi window */ 46*4882a593Smuzhiyun u64 dsnctl; /* matches definition of XSL_DSNCTL */ 47*4882a593Smuzhiyun u64 dra; /* real address that can be used for dummy read */ 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * Activate capi for the pci host bridge associated with the device. 55*4882a593Smuzhiyun * Can be extended to deactivate once we know how to do it. 56*4882a593Smuzhiyun * Device must be ready to accept messages from the CAPP unit and 57*4882a593Smuzhiyun * respond accordingly (TLB invalidates, ...) 58*4882a593Smuzhiyun * 59*4882a593Smuzhiyun * PHB is switched to capi mode through calls to skiboot. 60*4882a593Smuzhiyun * CAPP snooping is activated 61*4882a593Smuzhiyun * 62*4882a593Smuzhiyun * Input: 63*4882a593Smuzhiyun * dev: device whose PHB should switch mode 64*4882a593Smuzhiyun * mode: mode to switch to i.e. CAPI or PCI 65*4882a593Smuzhiyun * flags: options related to the mode 66*4882a593Smuzhiyun */ 67*4882a593Smuzhiyun enum cxllib_mode { 68*4882a593Smuzhiyun CXL_MODE_CXL, 69*4882a593Smuzhiyun CXL_MODE_PCI, 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define CXL_MODE_NO_DMA 0 73*4882a593Smuzhiyun #define CXL_MODE_DMA_TVT0 1 74*4882a593Smuzhiyun #define CXL_MODE_DMA_TVT1 2 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode, 77*4882a593Smuzhiyun unsigned long flags); 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* 81*4882a593Smuzhiyun * Set the device for capi DMA. 82*4882a593Smuzhiyun * Define its dma_ops and dma offset so that allocations will be using TVT#1 83*4882a593Smuzhiyun * 84*4882a593Smuzhiyun * Input: 85*4882a593Smuzhiyun * dev: device to set 86*4882a593Smuzhiyun * flags: options. CXL_MODE_DMA_TVT1 should be used 87*4882a593Smuzhiyun */ 88*4882a593Smuzhiyun int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * Get the Process Element structure for the given thread 93*4882a593Smuzhiyun * 94*4882a593Smuzhiyun * Input: 95*4882a593Smuzhiyun * task: task_struct for the context of the translation 96*4882a593Smuzhiyun * translation_mode: whether addresses should be translated 97*4882a593Smuzhiyun * Output: 98*4882a593Smuzhiyun * attr: attributes to fill up the Process Element structure from CAIA 99*4882a593Smuzhiyun */ 100*4882a593Smuzhiyun struct cxllib_pe_attributes { 101*4882a593Smuzhiyun u64 sr; 102*4882a593Smuzhiyun u32 lpid; 103*4882a593Smuzhiyun u32 tid; 104*4882a593Smuzhiyun u32 pid; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun #define CXL_TRANSLATED_MODE 0 107*4882a593Smuzhiyun #define CXL_REAL_MODE 1 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun int cxllib_get_PE_attributes(struct task_struct *task, 110*4882a593Smuzhiyun unsigned long translation_mode, struct cxllib_pe_attributes *attr); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* 114*4882a593Smuzhiyun * Handle memory fault. 115*4882a593Smuzhiyun * Fault in all the pages of the specified buffer for the permissions 116*4882a593Smuzhiyun * provided in ‘flags’ 117*4882a593Smuzhiyun * 118*4882a593Smuzhiyun * Shouldn't be called from interrupt context 119*4882a593Smuzhiyun * 120*4882a593Smuzhiyun * Input: 121*4882a593Smuzhiyun * mm: struct mm for the thread faulting the pages 122*4882a593Smuzhiyun * addr: base address of the buffer to page in 123*4882a593Smuzhiyun * size: size of the buffer to page in 124*4882a593Smuzhiyun * flags: permission requested (DSISR_ISSTORE...) 125*4882a593Smuzhiyun */ 126*4882a593Smuzhiyun int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags); 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #endif /* _MISC_CXLLIB_H */ 130