1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Renesas RPC-IF core driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2018~2019 Renesas Solutions Corp. 6*4882a593Smuzhiyun * Copyright (C) 2019 Macronix International Co., Ltd. 7*4882a593Smuzhiyun * Copyright (C) 2019-2020 Cogent Embedded, Inc. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __RENESAS_RPC_IF_H 11*4882a593Smuzhiyun #define __RENESAS_RPC_IF_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/types.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun enum rpcif_data_dir { 16*4882a593Smuzhiyun RPCIF_NO_DATA, 17*4882a593Smuzhiyun RPCIF_DATA_IN, 18*4882a593Smuzhiyun RPCIF_DATA_OUT, 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct rpcif_op { 22*4882a593Smuzhiyun struct { 23*4882a593Smuzhiyun u8 buswidth; 24*4882a593Smuzhiyun u8 opcode; 25*4882a593Smuzhiyun bool ddr; 26*4882a593Smuzhiyun } cmd, ocmd; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun struct { 29*4882a593Smuzhiyun u8 nbytes; 30*4882a593Smuzhiyun u8 buswidth; 31*4882a593Smuzhiyun bool ddr; 32*4882a593Smuzhiyun u64 val; 33*4882a593Smuzhiyun } addr; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct { 36*4882a593Smuzhiyun u8 ncycles; 37*4882a593Smuzhiyun u8 buswidth; 38*4882a593Smuzhiyun } dummy; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct { 41*4882a593Smuzhiyun u8 nbytes; 42*4882a593Smuzhiyun u8 buswidth; 43*4882a593Smuzhiyun bool ddr; 44*4882a593Smuzhiyun u32 val; 45*4882a593Smuzhiyun } option; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun struct { 48*4882a593Smuzhiyun u8 buswidth; 49*4882a593Smuzhiyun unsigned int nbytes; 50*4882a593Smuzhiyun enum rpcif_data_dir dir; 51*4882a593Smuzhiyun bool ddr; 52*4882a593Smuzhiyun union { 53*4882a593Smuzhiyun void *in; 54*4882a593Smuzhiyun const void *out; 55*4882a593Smuzhiyun } buf; 56*4882a593Smuzhiyun } data; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct rpcif { 60*4882a593Smuzhiyun struct device *dev; 61*4882a593Smuzhiyun void __iomem *base; 62*4882a593Smuzhiyun void __iomem *dirmap; 63*4882a593Smuzhiyun struct regmap *regmap; 64*4882a593Smuzhiyun struct reset_control *rstc; 65*4882a593Smuzhiyun size_t size; 66*4882a593Smuzhiyun enum rpcif_data_dir dir; 67*4882a593Smuzhiyun u8 bus_size; 68*4882a593Smuzhiyun u8 xfer_size; 69*4882a593Smuzhiyun void *buffer; 70*4882a593Smuzhiyun u32 xferlen; 71*4882a593Smuzhiyun u32 smcr; 72*4882a593Smuzhiyun u32 smadr; 73*4882a593Smuzhiyun u32 command; /* DRCMR or SMCMR */ 74*4882a593Smuzhiyun u32 option; /* DROPR or SMOPR */ 75*4882a593Smuzhiyun u32 enable; /* DRENR or SMENR */ 76*4882a593Smuzhiyun u32 dummy; /* DRDMCR or SMDMCR */ 77*4882a593Smuzhiyun u32 ddr; /* DRDRENR or SMDRENR */ 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun int rpcif_sw_init(struct rpcif *rpc, struct device *dev); 81*4882a593Smuzhiyun void rpcif_hw_init(struct rpcif *rpc, bool hyperflash); 82*4882a593Smuzhiyun void rpcif_enable_rpm(struct rpcif *rpc); 83*4882a593Smuzhiyun void rpcif_disable_rpm(struct rpcif *rpc); 84*4882a593Smuzhiyun void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs, 85*4882a593Smuzhiyun size_t *len); 86*4882a593Smuzhiyun int rpcif_manual_xfer(struct rpcif *rpc); 87*4882a593Smuzhiyun ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf); 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #endif // __RENESAS_RPC_IF_H 90