1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * vsp1.h -- R-Car VSP1 API 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Renesas Electronics Corporation 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun #ifndef __MEDIA_VSP1_H__ 10*4882a593Smuzhiyun #define __MEDIA_VSP1_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/scatterlist.h> 13*4882a593Smuzhiyun #include <linux/types.h> 14*4882a593Smuzhiyun #include <linux/videodev2.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun struct device; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun int vsp1_du_init(struct device *dev); 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define VSP1_DU_STATUS_COMPLETE BIT(0) 21*4882a593Smuzhiyun #define VSP1_DU_STATUS_WRITEBACK BIT(1) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /** 24*4882a593Smuzhiyun * struct vsp1_du_lif_config - VSP LIF configuration 25*4882a593Smuzhiyun * @width: output frame width 26*4882a593Smuzhiyun * @height: output frame height 27*4882a593Smuzhiyun * @interlaced: true for interlaced pipelines 28*4882a593Smuzhiyun * @callback: frame completion callback function (optional). When a callback 29*4882a593Smuzhiyun * is provided, the VSP driver guarantees that it will be called once 30*4882a593Smuzhiyun * and only once for each vsp1_du_atomic_flush() call. 31*4882a593Smuzhiyun * @callback_data: data to be passed to the frame completion callback 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun struct vsp1_du_lif_config { 34*4882a593Smuzhiyun unsigned int width; 35*4882a593Smuzhiyun unsigned int height; 36*4882a593Smuzhiyun bool interlaced; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun void (*callback)(void *data, unsigned int status, u32 crc); 39*4882a593Smuzhiyun void *callback_data; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index, 43*4882a593Smuzhiyun const struct vsp1_du_lif_config *cfg); 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /** 46*4882a593Smuzhiyun * struct vsp1_du_atomic_config - VSP atomic configuration parameters 47*4882a593Smuzhiyun * @pixelformat: plane pixel format (V4L2 4CC) 48*4882a593Smuzhiyun * @pitch: line pitch in bytes for the first plane 49*4882a593Smuzhiyun * @mem: DMA memory address for each plane of the frame buffer 50*4882a593Smuzhiyun * @src: source rectangle in the frame buffer (integer coordinates) 51*4882a593Smuzhiyun * @dst: destination rectangle on the display (integer coordinates) 52*4882a593Smuzhiyun * @alpha: alpha value (0: fully transparent, 255: fully opaque) 53*4882a593Smuzhiyun * @zpos: Z position of the plane (from 0 to number of planes minus 1) 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun struct vsp1_du_atomic_config { 56*4882a593Smuzhiyun u32 pixelformat; 57*4882a593Smuzhiyun unsigned int pitch; 58*4882a593Smuzhiyun dma_addr_t mem[3]; 59*4882a593Smuzhiyun struct v4l2_rect src; 60*4882a593Smuzhiyun struct v4l2_rect dst; 61*4882a593Smuzhiyun unsigned int alpha; 62*4882a593Smuzhiyun unsigned int zpos; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /** 66*4882a593Smuzhiyun * enum vsp1_du_crc_source - Source used for CRC calculation 67*4882a593Smuzhiyun * @VSP1_DU_CRC_NONE: CRC calculation disabled 68*4882a593Smuzhiyun * @VSP1_DU_CRC_PLANE: Perform CRC calculation on an input plane 69*4882a593Smuzhiyun * @VSP1_DU_CRC_OUTPUT: Perform CRC calculation on the composed output 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun enum vsp1_du_crc_source { 72*4882a593Smuzhiyun VSP1_DU_CRC_NONE, 73*4882a593Smuzhiyun VSP1_DU_CRC_PLANE, 74*4882a593Smuzhiyun VSP1_DU_CRC_OUTPUT, 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /** 78*4882a593Smuzhiyun * struct vsp1_du_crc_config - VSP CRC computation configuration parameters 79*4882a593Smuzhiyun * @source: source for CRC calculation 80*4882a593Smuzhiyun * @index: index of the CRC source plane (when source is set to plane) 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun struct vsp1_du_crc_config { 83*4882a593Smuzhiyun enum vsp1_du_crc_source source; 84*4882a593Smuzhiyun unsigned int index; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /** 88*4882a593Smuzhiyun * struct vsp1_du_writeback_config - VSP writeback configuration parameters 89*4882a593Smuzhiyun * @pixelformat: plane pixel format (V4L2 4CC) 90*4882a593Smuzhiyun * @pitch: line pitch in bytes for the first plane 91*4882a593Smuzhiyun * @mem: DMA memory address for each plane of the frame buffer 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun struct vsp1_du_writeback_config { 94*4882a593Smuzhiyun u32 pixelformat; 95*4882a593Smuzhiyun unsigned int pitch; 96*4882a593Smuzhiyun dma_addr_t mem[3]; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /** 100*4882a593Smuzhiyun * struct vsp1_du_atomic_pipe_config - VSP atomic pipe configuration parameters 101*4882a593Smuzhiyun * @crc: CRC computation configuration 102*4882a593Smuzhiyun * @writeback: writeback configuration 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun struct vsp1_du_atomic_pipe_config { 105*4882a593Smuzhiyun struct vsp1_du_crc_config crc; 106*4882a593Smuzhiyun struct vsp1_du_writeback_config writeback; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index); 110*4882a593Smuzhiyun int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index, 111*4882a593Smuzhiyun unsigned int rpf, 112*4882a593Smuzhiyun const struct vsp1_du_atomic_config *cfg); 113*4882a593Smuzhiyun void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index, 114*4882a593Smuzhiyun const struct vsp1_du_atomic_pipe_config *cfg); 115*4882a593Smuzhiyun int vsp1_du_map_sg(struct device *dev, struct sg_table *sgt); 116*4882a593Smuzhiyun void vsp1_du_unmap_sg(struct device *dev, struct sg_table *sgt); 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif /* __MEDIA_VSP1_H__ */ 119