1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tc358743 - Toshiba HDMI to CSI-2 bridge 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * References (c = chapter, p = page): 10*4882a593Smuzhiyun * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 11*4882a593Smuzhiyun * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _TC358743_ 15*4882a593Smuzhiyun #define _TC358743_ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun enum tc358743_ddc5v_delays { 18*4882a593Smuzhiyun DDC5V_DELAY_0_MS, 19*4882a593Smuzhiyun DDC5V_DELAY_50_MS, 20*4882a593Smuzhiyun DDC5V_DELAY_100_MS, 21*4882a593Smuzhiyun DDC5V_DELAY_200_MS, 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun enum tc358743_hdmi_detection_delay { 25*4882a593Smuzhiyun HDMI_MODE_DELAY_0_MS, 26*4882a593Smuzhiyun HDMI_MODE_DELAY_25_MS, 27*4882a593Smuzhiyun HDMI_MODE_DELAY_50_MS, 28*4882a593Smuzhiyun HDMI_MODE_DELAY_100_MS, 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun struct tc358743_platform_data { 32*4882a593Smuzhiyun /* System clock connected to REFCLK (pin H5) */ 33*4882a593Smuzhiyun u32 refclk_hz; /* 26 MHz, 27 MHz or 42 MHz */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* DDC +5V debounce delay to avoid spurious interrupts when the cable 36*4882a593Smuzhiyun * is connected. 37*4882a593Smuzhiyun * Sets DDC5V_MODE in register DDC_CTL. 38*4882a593Smuzhiyun * Default: DDC5V_DELAY_0_MS 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun enum tc358743_ddc5v_delays ddc5v_delay; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun bool enable_hdcp; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * The FIFO size is 512x32, so Toshiba recommend to set the default FIFO 46*4882a593Smuzhiyun * level to somewhere in the middle (e.g. 300), so it can cover speed 47*4882a593Smuzhiyun * mismatches in input and output ports. 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun u16 fifo_level; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */ 52*4882a593Smuzhiyun u16 pll_prd; 53*4882a593Smuzhiyun u16 pll_fbd; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* CSI 56*4882a593Smuzhiyun * Calculate CSI parameters with REF_02 for the highest resolution your 57*4882a593Smuzhiyun * CSI interface can handle. The driver will adjust the number of CSI 58*4882a593Smuzhiyun * lanes in use according to the pixel clock. 59*4882a593Smuzhiyun * 60*4882a593Smuzhiyun * The values in brackets are calculated with REF_02 when the number of 61*4882a593Smuzhiyun * bps pr lane is 823.5 MHz, and can serve as a starting point. 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun u32 lineinitcnt; /* (0x00001770) */ 64*4882a593Smuzhiyun u32 lptxtimecnt; /* (0x00000005) */ 65*4882a593Smuzhiyun u32 tclk_headercnt; /* (0x00001d04) */ 66*4882a593Smuzhiyun u32 tclk_trailcnt; /* (0x00000000) */ 67*4882a593Smuzhiyun u32 ths_headercnt; /* (0x00000505) */ 68*4882a593Smuzhiyun u32 twakeup; /* (0x00004650) */ 69*4882a593Smuzhiyun u32 tclk_postcnt; /* (0x00000000) */ 70*4882a593Smuzhiyun u32 ths_trailcnt; /* (0x00000004) */ 71*4882a593Smuzhiyun u32 hstxvregcnt; /* (0x00000005) */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* DVI->HDMI detection delay to avoid unnecessary switching between DVI 74*4882a593Smuzhiyun * and HDMI mode. 75*4882a593Smuzhiyun * Sets HDMI_DET_V in register HDMI_DET. 76*4882a593Smuzhiyun * Default: HDMI_MODE_DELAY_0_MS 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun enum tc358743_hdmi_detection_delay hdmi_detection_delay; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* Reset PHY automatically when TMDS clock goes from DC to AC. 81*4882a593Smuzhiyun * Sets PHY_AUTO_RST2 in register PHY_CTL2. 82*4882a593Smuzhiyun * Default: false 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun bool hdmi_phy_auto_reset_tmds_detected; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Reset PHY automatically when TMDS clock passes 21 MHz. 87*4882a593Smuzhiyun * Sets PHY_AUTO_RST3 in register PHY_CTL2. 88*4882a593Smuzhiyun * Default: false 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun bool hdmi_phy_auto_reset_tmds_in_range; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* Reset PHY automatically when TMDS clock is detected. 93*4882a593Smuzhiyun * Sets PHY_AUTO_RST4 in register PHY_CTL2. 94*4882a593Smuzhiyun * Default: false 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun bool hdmi_phy_auto_reset_tmds_valid; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Reset HDMI PHY automatically when hsync period is out of range. 99*4882a593Smuzhiyun * Sets H_PI_RST in register HV_RST. 100*4882a593Smuzhiyun * Default: false 101*4882a593Smuzhiyun */ 102*4882a593Smuzhiyun bool hdmi_phy_auto_reset_hsync_out_of_range; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Reset HDMI PHY automatically when vsync period is out of range. 105*4882a593Smuzhiyun * Sets V_PI_RST in register HV_RST. 106*4882a593Smuzhiyun * Default: false 107*4882a593Smuzhiyun */ 108*4882a593Smuzhiyun bool hdmi_phy_auto_reset_vsync_out_of_range; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* custom controls */ 112*4882a593Smuzhiyun /* Audio sample rate in Hz */ 113*4882a593Smuzhiyun #define TC358743_CID_AUDIO_SAMPLING_RATE (V4L2_CID_USER_TC358743_BASE + 0) 114*4882a593Smuzhiyun /* Audio present status */ 115*4882a593Smuzhiyun #define TC358743_CID_AUDIO_PRESENT (V4L2_CID_USER_TC358743_BASE + 1) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #endif 118