1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl) 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _SAA7115_H_ 10*4882a593Smuzhiyun #define _SAA7115_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* s_routing inputs, outputs, and config */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* SAA7111/3/4/5 HW inputs */ 15*4882a593Smuzhiyun #define SAA7115_COMPOSITE0 0 16*4882a593Smuzhiyun #define SAA7115_COMPOSITE1 1 17*4882a593Smuzhiyun #define SAA7115_COMPOSITE2 2 18*4882a593Smuzhiyun #define SAA7115_COMPOSITE3 3 19*4882a593Smuzhiyun #define SAA7115_COMPOSITE4 4 /* not available for the saa7111/3 */ 20*4882a593Smuzhiyun #define SAA7115_COMPOSITE5 5 /* not available for the saa7111/3 */ 21*4882a593Smuzhiyun #define SAA7115_SVIDEO0 6 22*4882a593Smuzhiyun #define SAA7115_SVIDEO1 7 23*4882a593Smuzhiyun #define SAA7115_SVIDEO2 8 24*4882a593Smuzhiyun #define SAA7115_SVIDEO3 9 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* outputs */ 27*4882a593Smuzhiyun #define SAA7115_IPORT_ON 1 28*4882a593Smuzhiyun #define SAA7115_IPORT_OFF 0 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* SAA7111 specific outputs. */ 31*4882a593Smuzhiyun #define SAA7111_VBI_BYPASS 2 32*4882a593Smuzhiyun #define SAA7111_FMT_YUV422 0x00 33*4882a593Smuzhiyun #define SAA7111_FMT_RGB 0x40 34*4882a593Smuzhiyun #define SAA7111_FMT_CCIR 0x80 35*4882a593Smuzhiyun #define SAA7111_FMT_YUV411 0xc0 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* config flags */ 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * Register 0x85 should set bit 0 to 0 (it's 1 by default). This bit 40*4882a593Smuzhiyun * controls the IDQ signal polarity which is set to 'inverted' if the bit 41*4882a593Smuzhiyun * it 1 and to 'default' if it is 0. 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun #define SAA7115_IDQ_IS_DEFAULT (1 << 0) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* s_crystal_freq values and flags */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* SAA7115 v4l2_crystal_freq frequency values */ 48*4882a593Smuzhiyun #define SAA7115_FREQ_32_11_MHZ 32110000 /* 32.11 MHz crystal, SAA7114/5 only */ 49*4882a593Smuzhiyun #define SAA7115_FREQ_24_576_MHZ 24576000 /* 24.576 MHz crystal */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* SAA7115 v4l2_crystal_freq audio clock control flags */ 52*4882a593Smuzhiyun #define SAA7115_FREQ_FL_UCGC (1 << 0) /* SA 3A[7], UCGC, SAA7115 only */ 53*4882a593Smuzhiyun #define SAA7115_FREQ_FL_CGCDIV (1 << 1) /* SA 3A[6], CGCDIV, SAA7115 only */ 54*4882a593Smuzhiyun #define SAA7115_FREQ_FL_APLL (1 << 2) /* SA 3A[3], APLL, SAA7114/5 only */ 55*4882a593Smuzhiyun #define SAA7115_FREQ_FL_DOUBLE_ASCLK (1 << 3) /* SA 39, LRDIV, SAA7114/5 only */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* ===== SAA7113 Config enums ===== */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Register 0x08 "Horizontal time constant" [Bit 3..4]: 60*4882a593Smuzhiyun * Should be set to "Fast Locking Mode" according to the datasheet, 61*4882a593Smuzhiyun * and that is the default setting in the gm7113c_init table. 62*4882a593Smuzhiyun * saa7113_init sets this value to "VTR Mode". */ 63*4882a593Smuzhiyun enum saa7113_r08_htc { 64*4882a593Smuzhiyun SAA7113_HTC_TV_MODE = 0x00, 65*4882a593Smuzhiyun SAA7113_HTC_VTR_MODE, /* Default for saa7113_init */ 66*4882a593Smuzhiyun SAA7113_HTC_FAST_LOCKING_MODE = 0x03 /* Default for gm7113c_init */ 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Register 0x10 "Output format selection" [Bit 6..7]: 70*4882a593Smuzhiyun * Defaults to ITU_656 as specified in datasheet. */ 71*4882a593Smuzhiyun enum saa7113_r10_ofts { 72*4882a593Smuzhiyun SAA7113_OFTS_ITU_656 = 0x0, /* Default */ 73*4882a593Smuzhiyun SAA7113_OFTS_VFLAG_BY_VREF, 74*4882a593Smuzhiyun SAA7113_OFTS_VFLAG_BY_DATA_TYPE 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * Register 0x12 "Output control" [Bit 0..3 Or Bit 4..7]: 79*4882a593Smuzhiyun * This is used to select what data is output on the RTS0 and RTS1 pins. 80*4882a593Smuzhiyun * RTS1 [Bit 4..7] Defaults to DOT_IN. (This value can not be set for RTS0) 81*4882a593Smuzhiyun * RTS0 [Bit 0..3] Defaults to VIPB in gm7113c_init as specified 82*4882a593Smuzhiyun * in the datasheet, but is set to HREF_HS in the saa7113_init table. 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun enum saa7113_r12_rts { 85*4882a593Smuzhiyun SAA7113_RTS_DOT_IN = 0, /* OBS: Only for RTS1 (Default RTS1) */ 86*4882a593Smuzhiyun SAA7113_RTS_VIPB, /* Default RTS0 For gm7113c_init */ 87*4882a593Smuzhiyun SAA7113_RTS_GPSW, 88*4882a593Smuzhiyun SAA7115_RTS_HL, 89*4882a593Smuzhiyun SAA7113_RTS_VL, 90*4882a593Smuzhiyun SAA7113_RTS_DL, 91*4882a593Smuzhiyun SAA7113_RTS_PLIN, 92*4882a593Smuzhiyun SAA7113_RTS_HREF_HS, /* Default RTS0 For saa7113_init */ 93*4882a593Smuzhiyun SAA7113_RTS_HS, 94*4882a593Smuzhiyun SAA7113_RTS_HQ, 95*4882a593Smuzhiyun SAA7113_RTS_ODD, 96*4882a593Smuzhiyun SAA7113_RTS_VS, 97*4882a593Smuzhiyun SAA7113_RTS_V123, 98*4882a593Smuzhiyun SAA7113_RTS_VGATE, 99*4882a593Smuzhiyun SAA7113_RTS_VREF, 100*4882a593Smuzhiyun SAA7113_RTS_FID 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /** 104*4882a593Smuzhiyun * struct saa7115_platform_data - Allow overriding default initialization 105*4882a593Smuzhiyun * 106*4882a593Smuzhiyun * @saa7113_force_gm7113c_init: Force the use of the gm7113c_init table 107*4882a593Smuzhiyun * instead of saa7113_init table 108*4882a593Smuzhiyun * (saa7113 only) 109*4882a593Smuzhiyun * @saa7113_r08_htc: [R_08 - Bit 3..4] 110*4882a593Smuzhiyun * @saa7113_r10_vrln: [R_10 - Bit 3] 111*4882a593Smuzhiyun * default: Disabled for gm7113c_init 112*4882a593Smuzhiyun * Enabled for saa7113c_init 113*4882a593Smuzhiyun * @saa7113_r10_ofts: [R_10 - Bit 6..7] 114*4882a593Smuzhiyun * @saa7113_r12_rts0: [R_12 - Bit 0..3] 115*4882a593Smuzhiyun * @saa7113_r12_rts1: [R_12 - Bit 4..7] 116*4882a593Smuzhiyun * @saa7113_r13_adlsb: [R_13 - Bit 7] - default: disabled 117*4882a593Smuzhiyun */ 118*4882a593Smuzhiyun struct saa7115_platform_data { 119*4882a593Smuzhiyun bool saa7113_force_gm7113c_init; 120*4882a593Smuzhiyun enum saa7113_r08_htc *saa7113_r08_htc; 121*4882a593Smuzhiyun bool *saa7113_r10_vrln; 122*4882a593Smuzhiyun enum saa7113_r10_ofts *saa7113_r10_ofts; 123*4882a593Smuzhiyun enum saa7113_r12_rts *saa7113_r12_rts0; 124*4882a593Smuzhiyun enum saa7113_r12_rts *saa7113_r12_rts1; 125*4882a593Smuzhiyun bool *saa7113_r13_adlsb; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #endif 129