1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef MT9P031_H 3*4882a593Smuzhiyun #define MT9P031_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun struct v4l2_subdev; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * struct mt9p031_platform_data - MT9P031 platform data 9*4882a593Smuzhiyun * @ext_freq: Input clock frequency 10*4882a593Smuzhiyun * @target_freq: Pixel clock frequency 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun struct mt9p031_platform_data { 13*4882a593Smuzhiyun int ext_freq; 14*4882a593Smuzhiyun int target_freq; 15*4882a593Smuzhiyun }; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #endif 18