1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * adv7604 - Analog Devices ADV7604 video decoder driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ADV7604_ 9*4882a593Smuzhiyun #define _ADV7604_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/types.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Analog input muxing modes (AFE register 0x02, [2:0]) */ 14*4882a593Smuzhiyun enum adv7604_ain_sel { 15*4882a593Smuzhiyun ADV7604_AIN1_2_3_NC_SYNC_1_2 = 0, 16*4882a593Smuzhiyun ADV7604_AIN4_5_6_NC_SYNC_2_1 = 1, 17*4882a593Smuzhiyun ADV7604_AIN7_8_9_NC_SYNC_3_1 = 2, 18*4882a593Smuzhiyun ADV7604_AIN10_11_12_NC_SYNC_4_1 = 3, 19*4882a593Smuzhiyun ADV7604_AIN9_4_5_6_SYNC_2_1 = 4, 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * Bus rotation and reordering. This is used to specify component reordering on 24*4882a593Smuzhiyun * the board and describes the components order on the bus when the ADV7604 25*4882a593Smuzhiyun * outputs RGB. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun enum adv7604_bus_order { 28*4882a593Smuzhiyun ADV7604_BUS_ORDER_RGB, /* No operation */ 29*4882a593Smuzhiyun ADV7604_BUS_ORDER_GRB, /* Swap 1-2 */ 30*4882a593Smuzhiyun ADV7604_BUS_ORDER_RBG, /* Swap 2-3 */ 31*4882a593Smuzhiyun ADV7604_BUS_ORDER_BGR, /* Swap 1-3 */ 32*4882a593Smuzhiyun ADV7604_BUS_ORDER_BRG, /* Rotate right */ 33*4882a593Smuzhiyun ADV7604_BUS_ORDER_GBR, /* Rotate left */ 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Input Color Space (IO register 0x02, [7:4]) */ 37*4882a593Smuzhiyun enum adv76xx_inp_color_space { 38*4882a593Smuzhiyun ADV76XX_INP_COLOR_SPACE_LIM_RGB = 0, 39*4882a593Smuzhiyun ADV76XX_INP_COLOR_SPACE_FULL_RGB = 1, 40*4882a593Smuzhiyun ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_601 = 2, 41*4882a593Smuzhiyun ADV76XX_INP_COLOR_SPACE_LIM_YCbCr_709 = 3, 42*4882a593Smuzhiyun ADV76XX_INP_COLOR_SPACE_XVYCC_601 = 4, 43*4882a593Smuzhiyun ADV76XX_INP_COLOR_SPACE_XVYCC_709 = 5, 44*4882a593Smuzhiyun ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_601 = 6, 45*4882a593Smuzhiyun ADV76XX_INP_COLOR_SPACE_FULL_YCbCr_709 = 7, 46*4882a593Smuzhiyun ADV76XX_INP_COLOR_SPACE_AUTO = 0xf, 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Select output format (IO register 0x03, [4:2]) */ 50*4882a593Smuzhiyun enum adv7604_op_format_mode_sel { 51*4882a593Smuzhiyun ADV7604_OP_FORMAT_MODE0 = 0x00, 52*4882a593Smuzhiyun ADV7604_OP_FORMAT_MODE1 = 0x04, 53*4882a593Smuzhiyun ADV7604_OP_FORMAT_MODE2 = 0x08, 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun enum adv76xx_drive_strength { 57*4882a593Smuzhiyun ADV76XX_DR_STR_MEDIUM_LOW = 1, 58*4882a593Smuzhiyun ADV76XX_DR_STR_MEDIUM_HIGH = 2, 59*4882a593Smuzhiyun ADV76XX_DR_STR_HIGH = 3, 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* INT1 Configuration (IO register 0x40, [1:0]) */ 63*4882a593Smuzhiyun enum adv76xx_int1_config { 64*4882a593Smuzhiyun ADV76XX_INT1_CONFIG_OPEN_DRAIN, 65*4882a593Smuzhiyun ADV76XX_INT1_CONFIG_ACTIVE_LOW, 66*4882a593Smuzhiyun ADV76XX_INT1_CONFIG_ACTIVE_HIGH, 67*4882a593Smuzhiyun ADV76XX_INT1_CONFIG_DISABLED, 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun enum adv76xx_page { 71*4882a593Smuzhiyun ADV76XX_PAGE_IO, 72*4882a593Smuzhiyun ADV7604_PAGE_AVLINK, 73*4882a593Smuzhiyun ADV76XX_PAGE_CEC, 74*4882a593Smuzhiyun ADV76XX_PAGE_INFOFRAME, 75*4882a593Smuzhiyun ADV7604_PAGE_ESDP, 76*4882a593Smuzhiyun ADV7604_PAGE_DPP, 77*4882a593Smuzhiyun ADV76XX_PAGE_AFE, 78*4882a593Smuzhiyun ADV76XX_PAGE_REP, 79*4882a593Smuzhiyun ADV76XX_PAGE_EDID, 80*4882a593Smuzhiyun ADV76XX_PAGE_HDMI, 81*4882a593Smuzhiyun ADV76XX_PAGE_TEST, 82*4882a593Smuzhiyun ADV76XX_PAGE_CP, 83*4882a593Smuzhiyun ADV7604_PAGE_VDP, 84*4882a593Smuzhiyun ADV76XX_PAGE_MAX, 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Platform dependent definition */ 88*4882a593Smuzhiyun struct adv76xx_platform_data { 89*4882a593Smuzhiyun /* DIS_PWRDNB: 1 if the PWRDNB pin is unused and unconnected */ 90*4882a593Smuzhiyun unsigned disable_pwrdnb:1; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* DIS_CABLE_DET_RST: 1 if the 5V pins are unused and unconnected */ 93*4882a593Smuzhiyun unsigned disable_cable_det_rst:1; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun int default_input; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* Analog input muxing mode */ 98*4882a593Smuzhiyun enum adv7604_ain_sel ain_sel; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* Bus rotation and reordering */ 101*4882a593Smuzhiyun enum adv7604_bus_order bus_order; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* Select output format mode */ 104*4882a593Smuzhiyun enum adv7604_op_format_mode_sel op_format_mode_sel; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Configuration of the INT1 pin */ 107*4882a593Smuzhiyun enum adv76xx_int1_config int1_config; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* IO register 0x02 */ 110*4882a593Smuzhiyun unsigned alt_gamma:1; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* IO register 0x05 */ 113*4882a593Smuzhiyun unsigned blank_data:1; 114*4882a593Smuzhiyun unsigned insert_av_codes:1; 115*4882a593Smuzhiyun unsigned replicate_av_codes:1; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* IO register 0x06 */ 118*4882a593Smuzhiyun unsigned inv_vs_pol:1; 119*4882a593Smuzhiyun unsigned inv_hs_pol:1; 120*4882a593Smuzhiyun unsigned inv_llc_pol:1; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* IO register 0x14 */ 123*4882a593Smuzhiyun enum adv76xx_drive_strength dr_str_data; 124*4882a593Smuzhiyun enum adv76xx_drive_strength dr_str_clk; 125*4882a593Smuzhiyun enum adv76xx_drive_strength dr_str_sync; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* IO register 0x30 */ 128*4882a593Smuzhiyun unsigned output_bus_lsb_to_msb:1; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun /* Free run */ 131*4882a593Smuzhiyun unsigned hdmi_free_run_mode; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* i2c addresses: 0 == use default */ 134*4882a593Smuzhiyun u8 i2c_addresses[ADV76XX_PAGE_MAX]; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun enum adv76xx_pad { 138*4882a593Smuzhiyun ADV76XX_PAD_HDMI_PORT_A = 0, 139*4882a593Smuzhiyun ADV7604_PAD_HDMI_PORT_B = 1, 140*4882a593Smuzhiyun ADV7604_PAD_HDMI_PORT_C = 2, 141*4882a593Smuzhiyun ADV7604_PAD_HDMI_PORT_D = 3, 142*4882a593Smuzhiyun ADV7604_PAD_VGA_RGB = 4, 143*4882a593Smuzhiyun ADV7604_PAD_VGA_COMP = 5, 144*4882a593Smuzhiyun /* The source pad is either 1 (ADV7611) or 6 (ADV7604) */ 145*4882a593Smuzhiyun ADV7604_PAD_SOURCE = 6, 146*4882a593Smuzhiyun ADV7611_PAD_SOURCE = 1, 147*4882a593Smuzhiyun ADV76XX_PAD_MAX = 7, 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE (V4L2_CID_DV_CLASS_BASE + 0x1000) 151*4882a593Smuzhiyun #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL (V4L2_CID_DV_CLASS_BASE + 0x1001) 152*4882a593Smuzhiyun #define V4L2_CID_ADV_RX_FREE_RUN_COLOR (V4L2_CID_DV_CLASS_BASE + 0x1002) 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* notify events */ 155*4882a593Smuzhiyun #define ADV76XX_HOTPLUG 1 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #endif 158