1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Samsung S5P/Exynos4 SoC series camera interface driver header
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 - 2013 Samsung Electronics Co., Ltd.
6*4882a593Smuzhiyun * Sylwester Nawrocki <s.nawrocki@samsung.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #ifndef S5P_FIMC_H_
10*4882a593Smuzhiyun #define S5P_FIMC_H_
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <media/media-entity.h>
13*4882a593Smuzhiyun #include <media/v4l2-dev.h>
14*4882a593Smuzhiyun #include <media/v4l2-mediabus.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * Enumeration of data inputs to the camera subsystem.
18*4882a593Smuzhiyun */
19*4882a593Smuzhiyun enum fimc_input {
20*4882a593Smuzhiyun FIMC_INPUT_PARALLEL_0 = 1,
21*4882a593Smuzhiyun FIMC_INPUT_PARALLEL_1,
22*4882a593Smuzhiyun FIMC_INPUT_MIPI_CSI2_0 = 3,
23*4882a593Smuzhiyun FIMC_INPUT_MIPI_CSI2_1,
24*4882a593Smuzhiyun FIMC_INPUT_WRITEBACK_A = 5,
25*4882a593Smuzhiyun FIMC_INPUT_WRITEBACK_B,
26*4882a593Smuzhiyun FIMC_INPUT_WRITEBACK_ISP = 5,
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * Enumeration of the FIMC data bus types.
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun enum fimc_bus_type {
33*4882a593Smuzhiyun /* Camera parallel bus */
34*4882a593Smuzhiyun FIMC_BUS_TYPE_ITU_601 = 1,
35*4882a593Smuzhiyun /* Camera parallel bus with embedded synchronization */
36*4882a593Smuzhiyun FIMC_BUS_TYPE_ITU_656,
37*4882a593Smuzhiyun /* Camera MIPI-CSI2 serial bus */
38*4882a593Smuzhiyun FIMC_BUS_TYPE_MIPI_CSI2,
39*4882a593Smuzhiyun /* FIFO link from LCD controller (WriteBack A) */
40*4882a593Smuzhiyun FIMC_BUS_TYPE_LCD_WRITEBACK_A,
41*4882a593Smuzhiyun /* FIFO link from LCD controller (WriteBack B) */
42*4882a593Smuzhiyun FIMC_BUS_TYPE_LCD_WRITEBACK_B,
43*4882a593Smuzhiyun /* FIFO link from FIMC-IS */
44*4882a593Smuzhiyun FIMC_BUS_TYPE_ISP_WRITEBACK = FIMC_BUS_TYPE_LCD_WRITEBACK_B,
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define fimc_input_is_parallel(x) ((x) == 1 || (x) == 2)
48*4882a593Smuzhiyun #define fimc_input_is_mipi_csi(x) ((x) == 3 || (x) == 4)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun * The subdevices' group IDs.
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun #define GRP_ID_SENSOR (1 << 8)
54*4882a593Smuzhiyun #define GRP_ID_FIMC_IS_SENSOR (1 << 9)
55*4882a593Smuzhiyun #define GRP_ID_WRITEBACK (1 << 10)
56*4882a593Smuzhiyun #define GRP_ID_CSIS (1 << 11)
57*4882a593Smuzhiyun #define GRP_ID_FIMC (1 << 12)
58*4882a593Smuzhiyun #define GRP_ID_FLITE (1 << 13)
59*4882a593Smuzhiyun #define GRP_ID_FIMC_IS (1 << 14)
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /**
62*4882a593Smuzhiyun * struct fimc_source_info - video source description required for the host
63*4882a593Smuzhiyun * interface configuration
64*4882a593Smuzhiyun *
65*4882a593Smuzhiyun * @fimc_bus_type: FIMC camera input type
66*4882a593Smuzhiyun * @sensor_bus_type: image sensor bus type, MIPI, ITU-R BT.601 etc.
67*4882a593Smuzhiyun * @flags: the parallel sensor bus flags defining signals polarity (V4L2_MBUS_*)
68*4882a593Smuzhiyun * @mux_id: FIMC camera interface multiplexer index (separate for MIPI and ITU)
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun struct fimc_source_info {
71*4882a593Smuzhiyun enum fimc_bus_type fimc_bus_type;
72*4882a593Smuzhiyun enum fimc_bus_type sensor_bus_type;
73*4882a593Smuzhiyun u16 flags;
74*4882a593Smuzhiyun u16 mux_id;
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun * v4l2_device notification id. This is only for internal use in the kernel.
79*4882a593Smuzhiyun * Sensor subdevs should issue S5P_FIMC_TX_END_NOTIFY notification in single
80*4882a593Smuzhiyun * frame capture mode when there is only one VSYNC pulse issued by the sensor
81*4882a593Smuzhiyun * at beginning of the frame transmission.
82*4882a593Smuzhiyun */
83*4882a593Smuzhiyun #define S5P_FIMC_TX_END_NOTIFY _IO('e', 0)
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define FIMC_MAX_PLANES 3
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /**
88*4882a593Smuzhiyun * struct fimc_fmt - color format data structure
89*4882a593Smuzhiyun * @mbus_code: media bus pixel code, -1 if not applicable
90*4882a593Smuzhiyun * @fourcc: fourcc code for this format, 0 if not applicable
91*4882a593Smuzhiyun * @color: the driver's private color format id
92*4882a593Smuzhiyun * @memplanes: number of physically non-contiguous data planes
93*4882a593Smuzhiyun * @colplanes: number of physically contiguous data planes
94*4882a593Smuzhiyun * @colorspace: v4l2 colorspace (V4L2_COLORSPACE_*)
95*4882a593Smuzhiyun * @depth: per plane driver's private 'number of bits per pixel'
96*4882a593Smuzhiyun * @mdataplanes: bitmask indicating meta data plane(s), (1 << plane_no)
97*4882a593Smuzhiyun * @flags: flags indicating which operation mode format applies to
98*4882a593Smuzhiyun */
99*4882a593Smuzhiyun struct fimc_fmt {
100*4882a593Smuzhiyun u32 mbus_code;
101*4882a593Smuzhiyun u32 fourcc;
102*4882a593Smuzhiyun u32 color;
103*4882a593Smuzhiyun u16 memplanes;
104*4882a593Smuzhiyun u16 colplanes;
105*4882a593Smuzhiyun u8 colorspace;
106*4882a593Smuzhiyun u8 depth[FIMC_MAX_PLANES];
107*4882a593Smuzhiyun u16 mdataplanes;
108*4882a593Smuzhiyun u16 flags;
109*4882a593Smuzhiyun #define FMT_FLAGS_CAM (1 << 0)
110*4882a593Smuzhiyun #define FMT_FLAGS_M2M_IN (1 << 1)
111*4882a593Smuzhiyun #define FMT_FLAGS_M2M_OUT (1 << 2)
112*4882a593Smuzhiyun #define FMT_FLAGS_M2M (1 << 1 | 1 << 2)
113*4882a593Smuzhiyun #define FMT_HAS_ALPHA (1 << 3)
114*4882a593Smuzhiyun #define FMT_FLAGS_COMPRESSED (1 << 4)
115*4882a593Smuzhiyun #define FMT_FLAGS_WRITEBACK (1 << 5)
116*4882a593Smuzhiyun #define FMT_FLAGS_RAW_BAYER (1 << 6)
117*4882a593Smuzhiyun #define FMT_FLAGS_YUV (1 << 7)
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun struct exynos_media_pipeline;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /*
123*4882a593Smuzhiyun * Media pipeline operations to be called from within a video node, i.e. the
124*4882a593Smuzhiyun * last entity within the pipeline. Implemented by related media device driver.
125*4882a593Smuzhiyun */
126*4882a593Smuzhiyun struct exynos_media_pipeline_ops {
127*4882a593Smuzhiyun int (*prepare)(struct exynos_media_pipeline *p,
128*4882a593Smuzhiyun struct media_entity *me);
129*4882a593Smuzhiyun int (*unprepare)(struct exynos_media_pipeline *p);
130*4882a593Smuzhiyun int (*open)(struct exynos_media_pipeline *p, struct media_entity *me,
131*4882a593Smuzhiyun bool resume);
132*4882a593Smuzhiyun int (*close)(struct exynos_media_pipeline *p);
133*4882a593Smuzhiyun int (*set_stream)(struct exynos_media_pipeline *p, bool state);
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun struct exynos_video_entity {
137*4882a593Smuzhiyun struct video_device vdev;
138*4882a593Smuzhiyun struct exynos_media_pipeline *pipe;
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun struct exynos_media_pipeline {
142*4882a593Smuzhiyun struct media_pipeline mp;
143*4882a593Smuzhiyun const struct exynos_media_pipeline_ops *ops;
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun
vdev_to_exynos_video_entity(struct video_device * vdev)146*4882a593Smuzhiyun static inline struct exynos_video_entity *vdev_to_exynos_video_entity(
147*4882a593Smuzhiyun struct video_device *vdev)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun return container_of(vdev, struct exynos_video_entity, vdev);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun #define fimc_pipeline_call(ent, op, args...) \
153*4882a593Smuzhiyun ((!(ent) || !(ent)->pipe) ? -ENOENT : \
154*4882a593Smuzhiyun (((ent)->pipe->ops && (ent)->pipe->ops->op) ? \
155*4882a593Smuzhiyun (ent)->pipe->ops->op(((ent)->pipe), ##args) : -ENOIOCTLCMD)) \
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun #endif /* S5P_FIMC_H_ */
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