1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2009 Texas Instruments Inc 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * vpss - video processing subsystem module header file. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Include this header file if a driver needs to configure vpss system 8*4882a593Smuzhiyun * module. It exports a set of library functions for video drivers to 9*4882a593Smuzhiyun * configure vpss system module functions such as clock enable/disable, 10*4882a593Smuzhiyun * vpss interrupt mux to arm, and other common vpss system module 11*4882a593Smuzhiyun * functions. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun #ifndef _VPSS_H 14*4882a593Smuzhiyun #define _VPSS_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* selector for ccdc input selection on DM355 */ 17*4882a593Smuzhiyun enum vpss_ccdc_source_sel { 18*4882a593Smuzhiyun VPSS_CCDCIN, 19*4882a593Smuzhiyun VPSS_HSSIIN, 20*4882a593Smuzhiyun VPSS_PGLPBK, /* for DM365 only */ 21*4882a593Smuzhiyun VPSS_CCDCPG /* for DM365 only */ 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct vpss_sync_pol { 25*4882a593Smuzhiyun unsigned int ccdpg_hdpol:1; 26*4882a593Smuzhiyun unsigned int ccdpg_vdpol:1; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct vpss_pg_frame_size { 30*4882a593Smuzhiyun short hlpfr; 31*4882a593Smuzhiyun short pplen; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Used for enable/disable VPSS Clock */ 35*4882a593Smuzhiyun enum vpss_clock_sel { 36*4882a593Smuzhiyun /* DM355/DM365 */ 37*4882a593Smuzhiyun VPSS_CCDC_CLOCK, 38*4882a593Smuzhiyun VPSS_IPIPE_CLOCK, 39*4882a593Smuzhiyun VPSS_H3A_CLOCK, 40*4882a593Smuzhiyun VPSS_CFALD_CLOCK, 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * When using VPSS_VENC_CLOCK_SEL in vpss_enable_clock() api 43*4882a593Smuzhiyun * following applies:- 44*4882a593Smuzhiyun * en = 0 selects ENC_CLK 45*4882a593Smuzhiyun * en = 1 selects ENC_CLK/2 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun VPSS_VENC_CLOCK_SEL, 48*4882a593Smuzhiyun VPSS_VPBE_CLOCK, 49*4882a593Smuzhiyun /* DM365 only clocks */ 50*4882a593Smuzhiyun VPSS_IPIPEIF_CLOCK, 51*4882a593Smuzhiyun VPSS_RSZ_CLOCK, 52*4882a593Smuzhiyun VPSS_BL_CLOCK, 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * When using VPSS_PCLK_INTERNAL in vpss_enable_clock() api 55*4882a593Smuzhiyun * following applies:- 56*4882a593Smuzhiyun * en = 0 disable internal PCLK 57*4882a593Smuzhiyun * en = 1 enables internal PCLK 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun VPSS_PCLK_INTERNAL, 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * When using VPSS_PSYNC_CLOCK_SEL in vpss_enable_clock() api 62*4882a593Smuzhiyun * following applies:- 63*4882a593Smuzhiyun * en = 0 enables MMR clock 64*4882a593Smuzhiyun * en = 1 enables VPSS clock 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun VPSS_PSYNC_CLOCK_SEL, 67*4882a593Smuzhiyun VPSS_LDC_CLOCK_SEL, 68*4882a593Smuzhiyun VPSS_OSD_CLOCK_SEL, 69*4882a593Smuzhiyun VPSS_FDIF_CLOCK, 70*4882a593Smuzhiyun VPSS_LDC_CLOCK 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* select input to ccdc on dm355 */ 74*4882a593Smuzhiyun int vpss_select_ccdc_source(enum vpss_ccdc_source_sel src_sel); 75*4882a593Smuzhiyun /* enable/disable a vpss clock, 0 - success, -1 - failure */ 76*4882a593Smuzhiyun int vpss_enable_clock(enum vpss_clock_sel clock_sel, int en); 77*4882a593Smuzhiyun /* set sync polarity, only for DM365*/ 78*4882a593Smuzhiyun void dm365_vpss_set_sync_pol(struct vpss_sync_pol); 79*4882a593Smuzhiyun /* set the PG_FRAME_SIZE register, only for DM365 */ 80*4882a593Smuzhiyun void dm365_vpss_set_pg_frame_size(struct vpss_pg_frame_size); 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* wbl reset for dm644x */ 83*4882a593Smuzhiyun enum vpss_wbl_sel { 84*4882a593Smuzhiyun VPSS_PCR_AEW_WBL_0 = 16, 85*4882a593Smuzhiyun VPSS_PCR_AF_WBL_0, 86*4882a593Smuzhiyun VPSS_PCR_RSZ4_WBL_0, 87*4882a593Smuzhiyun VPSS_PCR_RSZ3_WBL_0, 88*4882a593Smuzhiyun VPSS_PCR_RSZ2_WBL_0, 89*4882a593Smuzhiyun VPSS_PCR_RSZ1_WBL_0, 90*4882a593Smuzhiyun VPSS_PCR_PREV_WBL_0, 91*4882a593Smuzhiyun VPSS_PCR_CCDC_WBL_O, 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun /* clear wbl overflow flag for DM6446 */ 94*4882a593Smuzhiyun int vpss_clear_wbl_overflow(enum vpss_wbl_sel wbl_sel); 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* set sync polarity*/ 97*4882a593Smuzhiyun void vpss_set_sync_pol(struct vpss_sync_pol sync); 98*4882a593Smuzhiyun /* set the PG_FRAME_SIZE register */ 99*4882a593Smuzhiyun void vpss_set_pg_frame_size(struct vpss_pg_frame_size frame_size); 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * vpss_check_and_clear_interrupt - check and clear interrupt 102*4882a593Smuzhiyun * @irq - common enumerator for IRQ 103*4882a593Smuzhiyun * 104*4882a593Smuzhiyun * Following return values used:- 105*4882a593Smuzhiyun * 0 - interrupt occurred and cleared 106*4882a593Smuzhiyun * 1 - interrupt not occurred 107*4882a593Smuzhiyun * 2 - interrupt status not available 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun int vpss_dma_complete_interrupt(void); 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #endif 112