xref: /OK3568_Linux_fs/kernel/include/media/davinci/vpbe_osd.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2007-2009 Texas Instruments Inc
4*4882a593Smuzhiyun  * Copyright (C) 2007 MontaVista Software, Inc.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Andy Lowe (alowe@mvista.com), MontaVista Software
7*4882a593Smuzhiyun  * - Initial version
8*4882a593Smuzhiyun  * Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd.
9*4882a593Smuzhiyun  * - ported to sub device interface
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun #ifndef _OSD_H
12*4882a593Smuzhiyun #define _OSD_H
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <media/davinci/vpbe_types.h>
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #define DM644X_VPBE_OSD_SUBDEV_NAME	"dm644x,vpbe-osd"
17*4882a593Smuzhiyun #define DM365_VPBE_OSD_SUBDEV_NAME	"dm365,vpbe-osd"
18*4882a593Smuzhiyun #define DM355_VPBE_OSD_SUBDEV_NAME	"dm355,vpbe-osd"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /**
21*4882a593Smuzhiyun  * enum osd_layer
22*4882a593Smuzhiyun  * @WIN_OSD0: On-Screen Display Window 0
23*4882a593Smuzhiyun  * @WIN_VID0: Video Window 0
24*4882a593Smuzhiyun  * @WIN_OSD1: On-Screen Display Window 1
25*4882a593Smuzhiyun  * @WIN_VID1: Video Window 1
26*4882a593Smuzhiyun  *
27*4882a593Smuzhiyun  * Description:
28*4882a593Smuzhiyun  * An enumeration of the osd display layers.
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun enum osd_layer {
31*4882a593Smuzhiyun 	WIN_OSD0,
32*4882a593Smuzhiyun 	WIN_VID0,
33*4882a593Smuzhiyun 	WIN_OSD1,
34*4882a593Smuzhiyun 	WIN_VID1,
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /**
38*4882a593Smuzhiyun  * enum osd_win_layer
39*4882a593Smuzhiyun  * @OSDWIN_OSD0: On-Screen Display Window 0
40*4882a593Smuzhiyun  * @OSDWIN_OSD1: On-Screen Display Window 1
41*4882a593Smuzhiyun  *
42*4882a593Smuzhiyun  * Description:
43*4882a593Smuzhiyun  * An enumeration of the OSD Window layers.
44*4882a593Smuzhiyun  */
45*4882a593Smuzhiyun enum osd_win_layer {
46*4882a593Smuzhiyun 	OSDWIN_OSD0,
47*4882a593Smuzhiyun 	OSDWIN_OSD1,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /**
51*4882a593Smuzhiyun  * enum osd_pix_format
52*4882a593Smuzhiyun  * @PIXFMT_1BPP: 1-bit-per-pixel bitmap
53*4882a593Smuzhiyun  * @PIXFMT_2BPP: 2-bits-per-pixel bitmap
54*4882a593Smuzhiyun  * @PIXFMT_4BPP: 4-bits-per-pixel bitmap
55*4882a593Smuzhiyun  * @PIXFMT_8BPP: 8-bits-per-pixel bitmap
56*4882a593Smuzhiyun  * @PIXFMT_RGB565: 16-bits-per-pixel RGB565
57*4882a593Smuzhiyun  * @PIXFMT_YCbCrI: YUV 4:2:2
58*4882a593Smuzhiyun  * @PIXFMT_RGB888: 24-bits-per-pixel RGB888
59*4882a593Smuzhiyun  * @PIXFMT_YCrCbI: YUV 4:2:2 with chroma swap
60*4882a593Smuzhiyun  * @PIXFMT_NV12: YUV 4:2:0 planar
61*4882a593Smuzhiyun  * @PIXFMT_OSD_ATTR: OSD Attribute Window pixel format (4bpp)
62*4882a593Smuzhiyun  *
63*4882a593Smuzhiyun  * Description:
64*4882a593Smuzhiyun  * An enumeration of the DaVinci pixel formats.
65*4882a593Smuzhiyun  */
66*4882a593Smuzhiyun enum osd_pix_format {
67*4882a593Smuzhiyun 	PIXFMT_1BPP = 0,
68*4882a593Smuzhiyun 	PIXFMT_2BPP,
69*4882a593Smuzhiyun 	PIXFMT_4BPP,
70*4882a593Smuzhiyun 	PIXFMT_8BPP,
71*4882a593Smuzhiyun 	PIXFMT_RGB565,
72*4882a593Smuzhiyun 	PIXFMT_YCBCRI,
73*4882a593Smuzhiyun 	PIXFMT_RGB888,
74*4882a593Smuzhiyun 	PIXFMT_YCRCBI,
75*4882a593Smuzhiyun 	PIXFMT_NV12,
76*4882a593Smuzhiyun 	PIXFMT_OSD_ATTR,
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /**
80*4882a593Smuzhiyun  * enum osd_h_exp_ratio
81*4882a593Smuzhiyun  * @H_EXP_OFF: no expansion (1/1)
82*4882a593Smuzhiyun  * @H_EXP_9_OVER_8: 9/8 expansion ratio
83*4882a593Smuzhiyun  * @H_EXP_3_OVER_2: 3/2 expansion ratio
84*4882a593Smuzhiyun  *
85*4882a593Smuzhiyun  * Description:
86*4882a593Smuzhiyun  * An enumeration of the available horizontal expansion ratios.
87*4882a593Smuzhiyun  */
88*4882a593Smuzhiyun enum osd_h_exp_ratio {
89*4882a593Smuzhiyun 	H_EXP_OFF,
90*4882a593Smuzhiyun 	H_EXP_9_OVER_8,
91*4882a593Smuzhiyun 	H_EXP_3_OVER_2,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun /**
95*4882a593Smuzhiyun  * enum osd_v_exp_ratio
96*4882a593Smuzhiyun  * @V_EXP_OFF: no expansion (1/1)
97*4882a593Smuzhiyun  * @V_EXP_6_OVER_5: 6/5 expansion ratio
98*4882a593Smuzhiyun  *
99*4882a593Smuzhiyun  * Description:
100*4882a593Smuzhiyun  * An enumeration of the available vertical expansion ratios.
101*4882a593Smuzhiyun  */
102*4882a593Smuzhiyun enum osd_v_exp_ratio {
103*4882a593Smuzhiyun 	V_EXP_OFF,
104*4882a593Smuzhiyun 	V_EXP_6_OVER_5,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /**
108*4882a593Smuzhiyun  * enum osd_zoom_factor
109*4882a593Smuzhiyun  * @ZOOM_X1: no zoom (x1)
110*4882a593Smuzhiyun  * @ZOOM_X2: x2 zoom
111*4882a593Smuzhiyun  * @ZOOM_X4: x4 zoom
112*4882a593Smuzhiyun  *
113*4882a593Smuzhiyun  * Description:
114*4882a593Smuzhiyun  * An enumeration of the available zoom factors.
115*4882a593Smuzhiyun  */
116*4882a593Smuzhiyun enum osd_zoom_factor {
117*4882a593Smuzhiyun 	ZOOM_X1,
118*4882a593Smuzhiyun 	ZOOM_X2,
119*4882a593Smuzhiyun 	ZOOM_X4,
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /**
123*4882a593Smuzhiyun  * enum osd_clut
124*4882a593Smuzhiyun  * @ROM_CLUT: ROM CLUT
125*4882a593Smuzhiyun  * @RAM_CLUT: RAM CLUT
126*4882a593Smuzhiyun  *
127*4882a593Smuzhiyun  * Description:
128*4882a593Smuzhiyun  * An enumeration of the available Color Lookup Tables (CLUTs).
129*4882a593Smuzhiyun  */
130*4882a593Smuzhiyun enum osd_clut {
131*4882a593Smuzhiyun 	ROM_CLUT,
132*4882a593Smuzhiyun 	RAM_CLUT,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /**
136*4882a593Smuzhiyun  * enum osd_rom_clut
137*4882a593Smuzhiyun  * @ROM_CLUT0: Macintosh CLUT
138*4882a593Smuzhiyun  * @ROM_CLUT1: CLUT from DM270 and prior devices
139*4882a593Smuzhiyun  *
140*4882a593Smuzhiyun  * Description:
141*4882a593Smuzhiyun  * An enumeration of the ROM Color Lookup Table (CLUT) options.
142*4882a593Smuzhiyun  */
143*4882a593Smuzhiyun enum osd_rom_clut {
144*4882a593Smuzhiyun 	ROM_CLUT0,
145*4882a593Smuzhiyun 	ROM_CLUT1,
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun /**
149*4882a593Smuzhiyun  * enum osd_blending_factor
150*4882a593Smuzhiyun  * @OSD_0_VID_8: OSD pixels are fully transparent
151*4882a593Smuzhiyun  * @OSD_1_VID_7: OSD pixels contribute 1/8, video pixels contribute 7/8
152*4882a593Smuzhiyun  * @OSD_2_VID_6: OSD pixels contribute 2/8, video pixels contribute 6/8
153*4882a593Smuzhiyun  * @OSD_3_VID_5: OSD pixels contribute 3/8, video pixels contribute 5/8
154*4882a593Smuzhiyun  * @OSD_4_VID_4: OSD pixels contribute 4/8, video pixels contribute 4/8
155*4882a593Smuzhiyun  * @OSD_5_VID_3: OSD pixels contribute 5/8, video pixels contribute 3/8
156*4882a593Smuzhiyun  * @OSD_6_VID_2: OSD pixels contribute 6/8, video pixels contribute 2/8
157*4882a593Smuzhiyun  * @OSD_8_VID_0: OSD pixels are fully opaque
158*4882a593Smuzhiyun  *
159*4882a593Smuzhiyun  * Description:
160*4882a593Smuzhiyun  * An enumeration of the DaVinci pixel blending factor options.
161*4882a593Smuzhiyun  */
162*4882a593Smuzhiyun enum osd_blending_factor {
163*4882a593Smuzhiyun 	OSD_0_VID_8,
164*4882a593Smuzhiyun 	OSD_1_VID_7,
165*4882a593Smuzhiyun 	OSD_2_VID_6,
166*4882a593Smuzhiyun 	OSD_3_VID_5,
167*4882a593Smuzhiyun 	OSD_4_VID_4,
168*4882a593Smuzhiyun 	OSD_5_VID_3,
169*4882a593Smuzhiyun 	OSD_6_VID_2,
170*4882a593Smuzhiyun 	OSD_8_VID_0,
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /**
174*4882a593Smuzhiyun  * enum osd_blink_interval
175*4882a593Smuzhiyun  * @BLINK_X1: blink interval is 1 vertical refresh cycle
176*4882a593Smuzhiyun  * @BLINK_X2: blink interval is 2 vertical refresh cycles
177*4882a593Smuzhiyun  * @BLINK_X3: blink interval is 3 vertical refresh cycles
178*4882a593Smuzhiyun  * @BLINK_X4: blink interval is 4 vertical refresh cycles
179*4882a593Smuzhiyun  *
180*4882a593Smuzhiyun  * Description:
181*4882a593Smuzhiyun  * An enumeration of the DaVinci pixel blinking interval options.
182*4882a593Smuzhiyun  */
183*4882a593Smuzhiyun enum osd_blink_interval {
184*4882a593Smuzhiyun 	BLINK_X1,
185*4882a593Smuzhiyun 	BLINK_X2,
186*4882a593Smuzhiyun 	BLINK_X3,
187*4882a593Smuzhiyun 	BLINK_X4,
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun /**
191*4882a593Smuzhiyun  * enum osd_cursor_h_width
192*4882a593Smuzhiyun  * @H_WIDTH_1: horizontal line width is 1 pixel
193*4882a593Smuzhiyun  * @H_WIDTH_4: horizontal line width is 4 pixels
194*4882a593Smuzhiyun  * @H_WIDTH_8: horizontal line width is 8 pixels
195*4882a593Smuzhiyun  * @H_WIDTH_12: horizontal line width is 12 pixels
196*4882a593Smuzhiyun  * @H_WIDTH_16: horizontal line width is 16 pixels
197*4882a593Smuzhiyun  * @H_WIDTH_20: horizontal line width is 20 pixels
198*4882a593Smuzhiyun  * @H_WIDTH_24: horizontal line width is 24 pixels
199*4882a593Smuzhiyun  * @H_WIDTH_28: horizontal line width is 28 pixels
200*4882a593Smuzhiyun  */
201*4882a593Smuzhiyun enum osd_cursor_h_width {
202*4882a593Smuzhiyun 	H_WIDTH_1,
203*4882a593Smuzhiyun 	H_WIDTH_4,
204*4882a593Smuzhiyun 	H_WIDTH_8,
205*4882a593Smuzhiyun 	H_WIDTH_12,
206*4882a593Smuzhiyun 	H_WIDTH_16,
207*4882a593Smuzhiyun 	H_WIDTH_20,
208*4882a593Smuzhiyun 	H_WIDTH_24,
209*4882a593Smuzhiyun 	H_WIDTH_28,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun /**
213*4882a593Smuzhiyun  * enum davinci_cursor_v_width
214*4882a593Smuzhiyun  * @V_WIDTH_1: vertical line width is 1 line
215*4882a593Smuzhiyun  * @V_WIDTH_2: vertical line width is 2 lines
216*4882a593Smuzhiyun  * @V_WIDTH_4: vertical line width is 4 lines
217*4882a593Smuzhiyun  * @V_WIDTH_6: vertical line width is 6 lines
218*4882a593Smuzhiyun  * @V_WIDTH_8: vertical line width is 8 lines
219*4882a593Smuzhiyun  * @V_WIDTH_10: vertical line width is 10 lines
220*4882a593Smuzhiyun  * @V_WIDTH_12: vertical line width is 12 lines
221*4882a593Smuzhiyun  * @V_WIDTH_14: vertical line width is 14 lines
222*4882a593Smuzhiyun  */
223*4882a593Smuzhiyun enum osd_cursor_v_width {
224*4882a593Smuzhiyun 	V_WIDTH_1,
225*4882a593Smuzhiyun 	V_WIDTH_2,
226*4882a593Smuzhiyun 	V_WIDTH_4,
227*4882a593Smuzhiyun 	V_WIDTH_6,
228*4882a593Smuzhiyun 	V_WIDTH_8,
229*4882a593Smuzhiyun 	V_WIDTH_10,
230*4882a593Smuzhiyun 	V_WIDTH_12,
231*4882a593Smuzhiyun 	V_WIDTH_14,
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun /**
235*4882a593Smuzhiyun  * struct osd_cursor_config
236*4882a593Smuzhiyun  * @xsize: horizontal size in pixels
237*4882a593Smuzhiyun  * @ysize: vertical size in lines
238*4882a593Smuzhiyun  * @xpos: horizontal offset in pixels from the left edge of the display
239*4882a593Smuzhiyun  * @ypos: vertical offset in lines from the top of the display
240*4882a593Smuzhiyun  * @interlaced: Non-zero if the display is interlaced, or zero otherwise
241*4882a593Smuzhiyun  * @h_width: horizontal line width
242*4882a593Smuzhiyun  * @v_width: vertical line width
243*4882a593Smuzhiyun  * @clut: the CLUT selector (ROM or RAM) for the cursor color
244*4882a593Smuzhiyun  * @clut_index: an index into the CLUT for the cursor color
245*4882a593Smuzhiyun  *
246*4882a593Smuzhiyun  * Description:
247*4882a593Smuzhiyun  * A structure describing the configuration parameters of the hardware
248*4882a593Smuzhiyun  * rectangular cursor.
249*4882a593Smuzhiyun  */
250*4882a593Smuzhiyun struct osd_cursor_config {
251*4882a593Smuzhiyun 	unsigned xsize;
252*4882a593Smuzhiyun 	unsigned ysize;
253*4882a593Smuzhiyun 	unsigned xpos;
254*4882a593Smuzhiyun 	unsigned ypos;
255*4882a593Smuzhiyun 	int interlaced;
256*4882a593Smuzhiyun 	enum osd_cursor_h_width h_width;
257*4882a593Smuzhiyun 	enum osd_cursor_v_width v_width;
258*4882a593Smuzhiyun 	enum osd_clut clut;
259*4882a593Smuzhiyun 	unsigned char clut_index;
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun /**
263*4882a593Smuzhiyun  * struct osd_layer_config
264*4882a593Smuzhiyun  * @pixfmt: pixel format
265*4882a593Smuzhiyun  * @line_length: offset in bytes between start of each line in memory
266*4882a593Smuzhiyun  * @xsize: number of horizontal pixels displayed per line
267*4882a593Smuzhiyun  * @ysize: number of lines displayed
268*4882a593Smuzhiyun  * @xpos: horizontal offset in pixels from the left edge of the display
269*4882a593Smuzhiyun  * @ypos: vertical offset in lines from the top of the display
270*4882a593Smuzhiyun  * @interlaced: Non-zero if the display is interlaced, or zero otherwise
271*4882a593Smuzhiyun  *
272*4882a593Smuzhiyun  * Description:
273*4882a593Smuzhiyun  * A structure describing the configuration parameters of an On-Screen Display
274*4882a593Smuzhiyun  * (OSD) or video layer related to how the image is stored in memory.
275*4882a593Smuzhiyun  * @line_length must be a multiple of the cache line size (32 bytes).
276*4882a593Smuzhiyun  */
277*4882a593Smuzhiyun struct osd_layer_config {
278*4882a593Smuzhiyun 	enum osd_pix_format pixfmt;
279*4882a593Smuzhiyun 	unsigned line_length;
280*4882a593Smuzhiyun 	unsigned xsize;
281*4882a593Smuzhiyun 	unsigned ysize;
282*4882a593Smuzhiyun 	unsigned xpos;
283*4882a593Smuzhiyun 	unsigned ypos;
284*4882a593Smuzhiyun 	int interlaced;
285*4882a593Smuzhiyun };
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun /* parameters that apply on a per-window (OSD or video) basis */
288*4882a593Smuzhiyun struct osd_window_state {
289*4882a593Smuzhiyun 	int is_allocated;
290*4882a593Smuzhiyun 	int is_enabled;
291*4882a593Smuzhiyun 	unsigned long fb_base_phys;
292*4882a593Smuzhiyun 	enum osd_zoom_factor h_zoom;
293*4882a593Smuzhiyun 	enum osd_zoom_factor v_zoom;
294*4882a593Smuzhiyun 	struct osd_layer_config lconfig;
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun /* parameters that apply on a per-OSD-window basis */
298*4882a593Smuzhiyun struct osd_osdwin_state {
299*4882a593Smuzhiyun 	enum osd_clut clut;
300*4882a593Smuzhiyun 	enum osd_blending_factor blend;
301*4882a593Smuzhiyun 	int colorkey_blending;
302*4882a593Smuzhiyun 	unsigned colorkey;
303*4882a593Smuzhiyun 	int rec601_attenuation;
304*4882a593Smuzhiyun 	/* index is pixel value */
305*4882a593Smuzhiyun 	unsigned char palette_map[16];
306*4882a593Smuzhiyun };
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun /* hardware rectangular cursor parameters */
309*4882a593Smuzhiyun struct osd_cursor_state {
310*4882a593Smuzhiyun 	int is_enabled;
311*4882a593Smuzhiyun 	struct osd_cursor_config config;
312*4882a593Smuzhiyun };
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun struct osd_state;
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun struct vpbe_osd_ops {
317*4882a593Smuzhiyun 	int (*initialize)(struct osd_state *sd);
318*4882a593Smuzhiyun 	int (*request_layer)(struct osd_state *sd, enum osd_layer layer);
319*4882a593Smuzhiyun 	void (*release_layer)(struct osd_state *sd, enum osd_layer layer);
320*4882a593Smuzhiyun 	int (*enable_layer)(struct osd_state *sd, enum osd_layer layer,
321*4882a593Smuzhiyun 			    int otherwin);
322*4882a593Smuzhiyun 	void (*disable_layer)(struct osd_state *sd, enum osd_layer layer);
323*4882a593Smuzhiyun 	int (*set_layer_config)(struct osd_state *sd, enum osd_layer layer,
324*4882a593Smuzhiyun 				struct osd_layer_config *lconfig);
325*4882a593Smuzhiyun 	void (*get_layer_config)(struct osd_state *sd, enum osd_layer layer,
326*4882a593Smuzhiyun 				 struct osd_layer_config *lconfig);
327*4882a593Smuzhiyun 	void (*start_layer)(struct osd_state *sd, enum osd_layer layer,
328*4882a593Smuzhiyun 			    unsigned long fb_base_phys,
329*4882a593Smuzhiyun 			    unsigned long cbcr_ofst);
330*4882a593Smuzhiyun 	void (*set_left_margin)(struct osd_state *sd, u32 val);
331*4882a593Smuzhiyun 	void (*set_top_margin)(struct osd_state *sd, u32 val);
332*4882a593Smuzhiyun 	void (*set_interpolation_filter)(struct osd_state *sd, int filter);
333*4882a593Smuzhiyun 	int (*set_vid_expansion)(struct osd_state *sd,
334*4882a593Smuzhiyun 					enum osd_h_exp_ratio h_exp,
335*4882a593Smuzhiyun 					enum osd_v_exp_ratio v_exp);
336*4882a593Smuzhiyun 	void (*get_vid_expansion)(struct osd_state *sd,
337*4882a593Smuzhiyun 					enum osd_h_exp_ratio *h_exp,
338*4882a593Smuzhiyun 					enum osd_v_exp_ratio *v_exp);
339*4882a593Smuzhiyun 	void (*set_zoom)(struct osd_state *sd, enum osd_layer layer,
340*4882a593Smuzhiyun 				enum osd_zoom_factor h_zoom,
341*4882a593Smuzhiyun 				enum osd_zoom_factor v_zoom);
342*4882a593Smuzhiyun };
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun struct osd_state {
345*4882a593Smuzhiyun 	enum vpbe_version vpbe_type;
346*4882a593Smuzhiyun 	spinlock_t lock;
347*4882a593Smuzhiyun 	struct device *dev;
348*4882a593Smuzhiyun 	dma_addr_t osd_base_phys;
349*4882a593Smuzhiyun 	void __iomem *osd_base;
350*4882a593Smuzhiyun 	unsigned long osd_size;
351*4882a593Smuzhiyun 	/* 1-->the isr will toggle the VID0 ping-pong buffer */
352*4882a593Smuzhiyun 	int pingpong;
353*4882a593Smuzhiyun 	int interpolation_filter;
354*4882a593Smuzhiyun 	int field_inversion;
355*4882a593Smuzhiyun 	enum osd_h_exp_ratio osd_h_exp;
356*4882a593Smuzhiyun 	enum osd_v_exp_ratio osd_v_exp;
357*4882a593Smuzhiyun 	enum osd_h_exp_ratio vid_h_exp;
358*4882a593Smuzhiyun 	enum osd_v_exp_ratio vid_v_exp;
359*4882a593Smuzhiyun 	enum osd_clut backg_clut;
360*4882a593Smuzhiyun 	unsigned backg_clut_index;
361*4882a593Smuzhiyun 	enum osd_rom_clut rom_clut;
362*4882a593Smuzhiyun 	int is_blinking;
363*4882a593Smuzhiyun 	/* attribute window blinking enabled */
364*4882a593Smuzhiyun 	enum osd_blink_interval blink;
365*4882a593Smuzhiyun 	/* YCbCrI or YCrCbI */
366*4882a593Smuzhiyun 	enum osd_pix_format yc_pixfmt;
367*4882a593Smuzhiyun 	/* columns are Y, Cb, Cr */
368*4882a593Smuzhiyun 	unsigned char clut_ram[256][3];
369*4882a593Smuzhiyun 	struct osd_cursor_state cursor;
370*4882a593Smuzhiyun 	/* OSD0, VID0, OSD1, VID1 */
371*4882a593Smuzhiyun 	struct osd_window_state win[4];
372*4882a593Smuzhiyun 	/* OSD0, OSD1 */
373*4882a593Smuzhiyun 	struct osd_osdwin_state osdwin[2];
374*4882a593Smuzhiyun 	/* OSD device Operations */
375*4882a593Smuzhiyun 	struct vpbe_osd_ops ops;
376*4882a593Smuzhiyun };
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun struct osd_platform_data {
379*4882a593Smuzhiyun 	int  field_inv_wa_enable;
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun #endif
383