1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2008-2009 Texas Instruments Inc 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * isif header file 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _ISIF_H 8*4882a593Smuzhiyun #define _ISIF_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <media/davinci/ccdc_types.h> 11*4882a593Smuzhiyun #include <media/davinci/vpfe_types.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* isif float type S8Q8/U8Q8 */ 14*4882a593Smuzhiyun struct isif_float_8 { 15*4882a593Smuzhiyun /* 8 bit integer part */ 16*4882a593Smuzhiyun __u8 integer; 17*4882a593Smuzhiyun /* 8 bit decimal part */ 18*4882a593Smuzhiyun __u8 decimal; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* isif float type U16Q16/S16Q16 */ 22*4882a593Smuzhiyun struct isif_float_16 { 23*4882a593Smuzhiyun /* 16 bit integer part */ 24*4882a593Smuzhiyun __u16 integer; 25*4882a593Smuzhiyun /* 16 bit decimal part */ 26*4882a593Smuzhiyun __u16 decimal; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /************************************************************************ 30*4882a593Smuzhiyun * Vertical Defect Correction parameters 31*4882a593Smuzhiyun ***********************************************************************/ 32*4882a593Smuzhiyun /* Defect Correction (DFC) table entry */ 33*4882a593Smuzhiyun struct isif_vdfc_entry { 34*4882a593Smuzhiyun /* vertical position of defect */ 35*4882a593Smuzhiyun __u16 pos_vert; 36*4882a593Smuzhiyun /* horizontal position of defect */ 37*4882a593Smuzhiyun __u16 pos_horz; 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * Defect level of Vertical line defect position. This is subtracted 40*4882a593Smuzhiyun * from the data at the defect position 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun __u8 level_at_pos; 43*4882a593Smuzhiyun /* 44*4882a593Smuzhiyun * Defect level of the pixels upper than the vertical line defect. 45*4882a593Smuzhiyun * This is subtracted from the data 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun __u8 level_up_pixels; 48*4882a593Smuzhiyun /* 49*4882a593Smuzhiyun * Defect level of the pixels lower than the vertical line defect. 50*4882a593Smuzhiyun * This is subtracted from the data 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun __u8 level_low_pixels; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define ISIF_VDFC_TABLE_SIZE 8 56*4882a593Smuzhiyun struct isif_dfc { 57*4882a593Smuzhiyun /* enable vertical defect correction */ 58*4882a593Smuzhiyun __u8 en; 59*4882a593Smuzhiyun /* Defect level subtraction. Just fed through if saturating */ 60*4882a593Smuzhiyun #define ISIF_VDFC_NORMAL 0 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * Defect level subtraction. Horizontal interpolation ((i-2)+(i+2))/2 63*4882a593Smuzhiyun * if data saturating 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun #define ISIF_VDFC_HORZ_INTERPOL_IF_SAT 1 66*4882a593Smuzhiyun /* Horizontal interpolation (((i-2)+(i+2))/2) */ 67*4882a593Smuzhiyun #define ISIF_VDFC_HORZ_INTERPOL 2 68*4882a593Smuzhiyun /* one of the vertical defect correction modes above */ 69*4882a593Smuzhiyun __u8 corr_mode; 70*4882a593Smuzhiyun /* 0 - whole line corrected, 1 - not pixels upper than the defect */ 71*4882a593Smuzhiyun __u8 corr_whole_line; 72*4882a593Smuzhiyun #define ISIF_VDFC_NO_SHIFT 0 73*4882a593Smuzhiyun #define ISIF_VDFC_SHIFT_1 1 74*4882a593Smuzhiyun #define ISIF_VDFC_SHIFT_2 2 75*4882a593Smuzhiyun #define ISIF_VDFC_SHIFT_3 3 76*4882a593Smuzhiyun #define ISIF_VDFC_SHIFT_4 4 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * defect level shift value. level_at_pos, level_upper_pos, 79*4882a593Smuzhiyun * and level_lower_pos can be shifted up by this value. Choose 80*4882a593Smuzhiyun * one of the values above 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun __u8 def_level_shift; 83*4882a593Smuzhiyun /* defect saturation level */ 84*4882a593Smuzhiyun __u16 def_sat_level; 85*4882a593Smuzhiyun /* number of vertical defects. Max is ISIF_VDFC_TABLE_SIZE */ 86*4882a593Smuzhiyun __u16 num_vdefects; 87*4882a593Smuzhiyun /* VDFC table ptr */ 88*4882a593Smuzhiyun struct isif_vdfc_entry table[ISIF_VDFC_TABLE_SIZE]; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun struct isif_horz_bclamp { 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Horizontal clamp disabled. Only vertical clamp value is subtracted */ 94*4882a593Smuzhiyun #define ISIF_HORZ_BC_DISABLE 0 95*4882a593Smuzhiyun /* 96*4882a593Smuzhiyun * Horizontal clamp value is calculated and subtracted from image data 97*4882a593Smuzhiyun * along with vertical clamp value 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun #define ISIF_HORZ_BC_CLAMP_CALC_ENABLED 1 100*4882a593Smuzhiyun /* 101*4882a593Smuzhiyun * Horizontal clamp value calculated from previous image is subtracted 102*4882a593Smuzhiyun * from image data along with vertical clamp value. 103*4882a593Smuzhiyun */ 104*4882a593Smuzhiyun #define ISIF_HORZ_BC_CLAMP_NOT_UPDATED 2 105*4882a593Smuzhiyun /* horizontal clamp mode. One of the values above */ 106*4882a593Smuzhiyun __u8 mode; 107*4882a593Smuzhiyun /* 108*4882a593Smuzhiyun * pixel value limit enable. 109*4882a593Smuzhiyun * 0 - limit disabled 110*4882a593Smuzhiyun * 1 - pixel value limited to 1023 111*4882a593Smuzhiyun */ 112*4882a593Smuzhiyun __u8 clamp_pix_limit; 113*4882a593Smuzhiyun /* Select Most left window for bc calculation */ 114*4882a593Smuzhiyun #define ISIF_SEL_MOST_LEFT_WIN 0 115*4882a593Smuzhiyun /* Select Most right window for bc calculation */ 116*4882a593Smuzhiyun #define ISIF_SEL_MOST_RIGHT_WIN 1 117*4882a593Smuzhiyun /* Select most left or right window for clamp val calculation */ 118*4882a593Smuzhiyun __u8 base_win_sel_calc; 119*4882a593Smuzhiyun /* Window count per color for calculation. range 1-32 */ 120*4882a593Smuzhiyun __u8 win_count_calc; 121*4882a593Smuzhiyun /* Window start position - horizontal for calculation. 0 - 8191 */ 122*4882a593Smuzhiyun __u16 win_start_h_calc; 123*4882a593Smuzhiyun /* Window start position - vertical for calculation 0 - 8191 */ 124*4882a593Smuzhiyun __u16 win_start_v_calc; 125*4882a593Smuzhiyun #define ISIF_HORZ_BC_SZ_H_2PIXELS 0 126*4882a593Smuzhiyun #define ISIF_HORZ_BC_SZ_H_4PIXELS 1 127*4882a593Smuzhiyun #define ISIF_HORZ_BC_SZ_H_8PIXELS 2 128*4882a593Smuzhiyun #define ISIF_HORZ_BC_SZ_H_16PIXELS 3 129*4882a593Smuzhiyun /* Width of the sample window in pixels for calculation */ 130*4882a593Smuzhiyun __u8 win_h_sz_calc; 131*4882a593Smuzhiyun #define ISIF_HORZ_BC_SZ_V_32PIXELS 0 132*4882a593Smuzhiyun #define ISIF_HORZ_BC_SZ_V_64PIXELS 1 133*4882a593Smuzhiyun #define ISIF_HORZ_BC_SZ_V_128PIXELS 2 134*4882a593Smuzhiyun #define ISIF_HORZ_BC_SZ_V_256PIXELS 3 135*4882a593Smuzhiyun /* Height of the sample window in pixels for calculation */ 136*4882a593Smuzhiyun __u8 win_v_sz_calc; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun /************************************************************************ 140*4882a593Smuzhiyun * Black Clamp parameters 141*4882a593Smuzhiyun ***********************************************************************/ 142*4882a593Smuzhiyun struct isif_vert_bclamp { 143*4882a593Smuzhiyun /* Reset value used is the clamp value calculated */ 144*4882a593Smuzhiyun #define ISIF_VERT_BC_USE_HORZ_CLAMP_VAL 0 145*4882a593Smuzhiyun /* Reset value used is reset_clamp_val configured */ 146*4882a593Smuzhiyun #define ISIF_VERT_BC_USE_CONFIG_CLAMP_VAL 1 147*4882a593Smuzhiyun /* No update, previous image value is used */ 148*4882a593Smuzhiyun #define ISIF_VERT_BC_NO_UPDATE 2 149*4882a593Smuzhiyun /* 150*4882a593Smuzhiyun * Reset value selector for vertical clamp calculation. Use one of 151*4882a593Smuzhiyun * the above values 152*4882a593Smuzhiyun */ 153*4882a593Smuzhiyun __u8 reset_val_sel; 154*4882a593Smuzhiyun /* U8Q8. Line average coefficient used in vertical clamp calculation */ 155*4882a593Smuzhiyun __u8 line_ave_coef; 156*4882a593Smuzhiyun /* Height of the optical black region for calculation */ 157*4882a593Smuzhiyun __u16 ob_v_sz_calc; 158*4882a593Smuzhiyun /* Optical black region start position - horizontal. 0 - 8191 */ 159*4882a593Smuzhiyun __u16 ob_start_h; 160*4882a593Smuzhiyun /* Optical black region start position - vertical 0 - 8191 */ 161*4882a593Smuzhiyun __u16 ob_start_v; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun struct isif_black_clamp { 165*4882a593Smuzhiyun /* 166*4882a593Smuzhiyun * This offset value is added irrespective of the clamp enable status. 167*4882a593Smuzhiyun * S13 168*4882a593Smuzhiyun */ 169*4882a593Smuzhiyun __u16 dc_offset; 170*4882a593Smuzhiyun /* 171*4882a593Smuzhiyun * Enable black/digital clamp value to be subtracted from the image data 172*4882a593Smuzhiyun */ 173*4882a593Smuzhiyun __u8 en; 174*4882a593Smuzhiyun /* 175*4882a593Smuzhiyun * black clamp mode. same/separate clamp for 4 colors 176*4882a593Smuzhiyun * 0 - disable - same clamp value for all colors 177*4882a593Smuzhiyun * 1 - clamp value calculated separately for all colors 178*4882a593Smuzhiyun */ 179*4882a593Smuzhiyun __u8 bc_mode_color; 180*4882a593Smuzhiyun /* Vrtical start position for bc subtraction */ 181*4882a593Smuzhiyun __u16 vert_start_sub; 182*4882a593Smuzhiyun /* Black clamp for horizontal direction */ 183*4882a593Smuzhiyun struct isif_horz_bclamp horz; 184*4882a593Smuzhiyun /* Black clamp for vertical direction */ 185*4882a593Smuzhiyun struct isif_vert_bclamp vert; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /************************************************************************* 189*4882a593Smuzhiyun ** Color Space Conversion (CSC) 190*4882a593Smuzhiyun *************************************************************************/ 191*4882a593Smuzhiyun #define ISIF_CSC_NUM_COEFF 16 192*4882a593Smuzhiyun struct isif_color_space_conv { 193*4882a593Smuzhiyun /* Enable color space conversion */ 194*4882a593Smuzhiyun __u8 en; 195*4882a593Smuzhiyun /* 196*4882a593Smuzhiyun * csc coeffient table. S8Q5, M00 at index 0, M01 at index 1, and 197*4882a593Smuzhiyun * so forth 198*4882a593Smuzhiyun */ 199*4882a593Smuzhiyun struct isif_float_8 coeff[ISIF_CSC_NUM_COEFF]; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /************************************************************************* 204*4882a593Smuzhiyun ** Black Compensation parameters 205*4882a593Smuzhiyun *************************************************************************/ 206*4882a593Smuzhiyun struct isif_black_comp { 207*4882a593Smuzhiyun /* Comp for Red */ 208*4882a593Smuzhiyun __s8 r_comp; 209*4882a593Smuzhiyun /* Comp for Gr */ 210*4882a593Smuzhiyun __s8 gr_comp; 211*4882a593Smuzhiyun /* Comp for Blue */ 212*4882a593Smuzhiyun __s8 b_comp; 213*4882a593Smuzhiyun /* Comp for Gb */ 214*4882a593Smuzhiyun __s8 gb_comp; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /************************************************************************* 218*4882a593Smuzhiyun ** Gain parameters 219*4882a593Smuzhiyun *************************************************************************/ 220*4882a593Smuzhiyun struct isif_gain { 221*4882a593Smuzhiyun /* Gain for Red or ye */ 222*4882a593Smuzhiyun struct isif_float_16 r_ye; 223*4882a593Smuzhiyun /* Gain for Gr or cy */ 224*4882a593Smuzhiyun struct isif_float_16 gr_cy; 225*4882a593Smuzhiyun /* Gain for Gb or g */ 226*4882a593Smuzhiyun struct isif_float_16 gb_g; 227*4882a593Smuzhiyun /* Gain for Blue or mg */ 228*4882a593Smuzhiyun struct isif_float_16 b_mg; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define ISIF_LINEAR_TAB_SIZE 192 232*4882a593Smuzhiyun /************************************************************************* 233*4882a593Smuzhiyun ** Linearization parameters 234*4882a593Smuzhiyun *************************************************************************/ 235*4882a593Smuzhiyun struct isif_linearize { 236*4882a593Smuzhiyun /* Enable or Disable linearization of data */ 237*4882a593Smuzhiyun __u8 en; 238*4882a593Smuzhiyun /* Shift value applied */ 239*4882a593Smuzhiyun __u8 corr_shft; 240*4882a593Smuzhiyun /* scale factor applied U11Q10 */ 241*4882a593Smuzhiyun struct isif_float_16 scale_fact; 242*4882a593Smuzhiyun /* Size of the linear table */ 243*4882a593Smuzhiyun __u16 table[ISIF_LINEAR_TAB_SIZE]; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* Color patterns */ 247*4882a593Smuzhiyun #define ISIF_RED 0 248*4882a593Smuzhiyun #define ISIF_GREEN_RED 1 249*4882a593Smuzhiyun #define ISIF_GREEN_BLUE 2 250*4882a593Smuzhiyun #define ISIF_BLUE 3 251*4882a593Smuzhiyun struct isif_col_pat { 252*4882a593Smuzhiyun __u8 olop; 253*4882a593Smuzhiyun __u8 olep; 254*4882a593Smuzhiyun __u8 elop; 255*4882a593Smuzhiyun __u8 elep; 256*4882a593Smuzhiyun }; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun /************************************************************************* 259*4882a593Smuzhiyun ** Data formatter parameters 260*4882a593Smuzhiyun *************************************************************************/ 261*4882a593Smuzhiyun struct isif_fmtplen { 262*4882a593Smuzhiyun /* 263*4882a593Smuzhiyun * number of program entries for SET0, range 1 - 16 264*4882a593Smuzhiyun * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is 265*4882a593Smuzhiyun * ISIF_COMBINE 266*4882a593Smuzhiyun */ 267*4882a593Smuzhiyun __u16 plen0; 268*4882a593Smuzhiyun /* 269*4882a593Smuzhiyun * number of program entries for SET1, range 1 - 16 270*4882a593Smuzhiyun * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is 271*4882a593Smuzhiyun * ISIF_COMBINE 272*4882a593Smuzhiyun */ 273*4882a593Smuzhiyun __u16 plen1; 274*4882a593Smuzhiyun /** 275*4882a593Smuzhiyun * number of program entries for SET2, range 1 - 16 276*4882a593Smuzhiyun * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is 277*4882a593Smuzhiyun * ISIF_COMBINE 278*4882a593Smuzhiyun */ 279*4882a593Smuzhiyun __u16 plen2; 280*4882a593Smuzhiyun /** 281*4882a593Smuzhiyun * number of program entries for SET3, range 1 - 16 282*4882a593Smuzhiyun * when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is 283*4882a593Smuzhiyun * ISIF_COMBINE 284*4882a593Smuzhiyun */ 285*4882a593Smuzhiyun __u16 plen3; 286*4882a593Smuzhiyun }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun struct isif_fmt_cfg { 289*4882a593Smuzhiyun #define ISIF_SPLIT 0 290*4882a593Smuzhiyun #define ISIF_COMBINE 1 291*4882a593Smuzhiyun /* Split or combine or line alternate */ 292*4882a593Smuzhiyun __u8 fmtmode; 293*4882a593Smuzhiyun /* enable or disable line alternating mode */ 294*4882a593Smuzhiyun __u8 ln_alter_en; 295*4882a593Smuzhiyun #define ISIF_1LINE 0 296*4882a593Smuzhiyun #define ISIF_2LINES 1 297*4882a593Smuzhiyun #define ISIF_3LINES 2 298*4882a593Smuzhiyun #define ISIF_4LINES 3 299*4882a593Smuzhiyun /* Split/combine line number */ 300*4882a593Smuzhiyun __u8 lnum; 301*4882a593Smuzhiyun /* Address increment Range 1 - 16 */ 302*4882a593Smuzhiyun __u8 addrinc; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun struct isif_fmt_addr_ptr { 306*4882a593Smuzhiyun /* Initial address */ 307*4882a593Smuzhiyun __u32 init_addr; 308*4882a593Smuzhiyun /* output line number */ 309*4882a593Smuzhiyun #define ISIF_1STLINE 0 310*4882a593Smuzhiyun #define ISIF_2NDLINE 1 311*4882a593Smuzhiyun #define ISIF_3RDLINE 2 312*4882a593Smuzhiyun #define ISIF_4THLINE 3 313*4882a593Smuzhiyun __u8 out_line; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun struct isif_fmtpgm_ap { 317*4882a593Smuzhiyun /* program address pointer */ 318*4882a593Smuzhiyun __u8 pgm_aptr; 319*4882a593Smuzhiyun /* program address increment or decrement */ 320*4882a593Smuzhiyun __u8 pgmupdt; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun struct isif_data_formatter { 324*4882a593Smuzhiyun /* Enable/Disable data formatter */ 325*4882a593Smuzhiyun __u8 en; 326*4882a593Smuzhiyun /* data formatter configuration */ 327*4882a593Smuzhiyun struct isif_fmt_cfg cfg; 328*4882a593Smuzhiyun /* Formatter program entries length */ 329*4882a593Smuzhiyun struct isif_fmtplen plen; 330*4882a593Smuzhiyun /* first pixel in a line fed to formatter */ 331*4882a593Smuzhiyun __u16 fmtrlen; 332*4882a593Smuzhiyun /* HD interval for output line. Only valid when split line */ 333*4882a593Smuzhiyun __u16 fmthcnt; 334*4882a593Smuzhiyun /* formatter address pointers */ 335*4882a593Smuzhiyun struct isif_fmt_addr_ptr fmtaddr_ptr[16]; 336*4882a593Smuzhiyun /* program enable/disable */ 337*4882a593Smuzhiyun __u8 pgm_en[32]; 338*4882a593Smuzhiyun /* program address pointers */ 339*4882a593Smuzhiyun struct isif_fmtpgm_ap fmtpgm_ap[32]; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun struct isif_df_csc { 343*4882a593Smuzhiyun /* Color Space Conversion confguration, 0 - csc, 1 - df */ 344*4882a593Smuzhiyun __u8 df_or_csc; 345*4882a593Smuzhiyun /* csc configuration valid if df_or_csc is 0 */ 346*4882a593Smuzhiyun struct isif_color_space_conv csc; 347*4882a593Smuzhiyun /* data formatter configuration valid if df_or_csc is 1 */ 348*4882a593Smuzhiyun struct isif_data_formatter df; 349*4882a593Smuzhiyun /* start pixel in a line at the input */ 350*4882a593Smuzhiyun __u32 start_pix; 351*4882a593Smuzhiyun /* number of pixels in input line */ 352*4882a593Smuzhiyun __u32 num_pixels; 353*4882a593Smuzhiyun /* start line at the input */ 354*4882a593Smuzhiyun __u32 start_line; 355*4882a593Smuzhiyun /* number of lines at the input */ 356*4882a593Smuzhiyun __u32 num_lines; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun struct isif_gain_offsets_adj { 360*4882a593Smuzhiyun /* Gain adjustment per color */ 361*4882a593Smuzhiyun struct isif_gain gain; 362*4882a593Smuzhiyun /* Offset adjustment */ 363*4882a593Smuzhiyun __u16 offset; 364*4882a593Smuzhiyun /* Enable or Disable Gain adjustment for SDRAM data */ 365*4882a593Smuzhiyun __u8 gain_sdram_en; 366*4882a593Smuzhiyun /* Enable or Disable Gain adjustment for IPIPE data */ 367*4882a593Smuzhiyun __u8 gain_ipipe_en; 368*4882a593Smuzhiyun /* Enable or Disable Gain adjustment for H3A data */ 369*4882a593Smuzhiyun __u8 gain_h3a_en; 370*4882a593Smuzhiyun /* Enable or Disable Gain adjustment for SDRAM data */ 371*4882a593Smuzhiyun __u8 offset_sdram_en; 372*4882a593Smuzhiyun /* Enable or Disable Gain adjustment for IPIPE data */ 373*4882a593Smuzhiyun __u8 offset_ipipe_en; 374*4882a593Smuzhiyun /* Enable or Disable Gain adjustment for H3A data */ 375*4882a593Smuzhiyun __u8 offset_h3a_en; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun struct isif_cul { 379*4882a593Smuzhiyun /* Horizontal Cull pattern for odd lines */ 380*4882a593Smuzhiyun __u8 hcpat_odd; 381*4882a593Smuzhiyun /* Horizontal Cull pattern for even lines */ 382*4882a593Smuzhiyun __u8 hcpat_even; 383*4882a593Smuzhiyun /* Vertical Cull pattern */ 384*4882a593Smuzhiyun __u8 vcpat; 385*4882a593Smuzhiyun /* Enable or disable lpf. Apply when cull is enabled */ 386*4882a593Smuzhiyun __u8 en_lpf; 387*4882a593Smuzhiyun }; 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun struct isif_compress { 390*4882a593Smuzhiyun #define ISIF_ALAW 0 391*4882a593Smuzhiyun #define ISIF_DPCM 1 392*4882a593Smuzhiyun #define ISIF_NO_COMPRESSION 2 393*4882a593Smuzhiyun /* Compression Algorithm used */ 394*4882a593Smuzhiyun __u8 alg; 395*4882a593Smuzhiyun /* Choose Predictor1 for DPCM compression */ 396*4882a593Smuzhiyun #define ISIF_DPCM_PRED1 0 397*4882a593Smuzhiyun /* Choose Predictor2 for DPCM compression */ 398*4882a593Smuzhiyun #define ISIF_DPCM_PRED2 1 399*4882a593Smuzhiyun /* Predictor for DPCM compression */ 400*4882a593Smuzhiyun __u8 pred; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun /* all the stuff in this struct will be provided by userland */ 404*4882a593Smuzhiyun struct isif_config_params_raw { 405*4882a593Smuzhiyun /* Linearization parameters for image sensor data input */ 406*4882a593Smuzhiyun struct isif_linearize linearize; 407*4882a593Smuzhiyun /* Data formatter or CSC */ 408*4882a593Smuzhiyun struct isif_df_csc df_csc; 409*4882a593Smuzhiyun /* Defect Pixel Correction (DFC) confguration */ 410*4882a593Smuzhiyun struct isif_dfc dfc; 411*4882a593Smuzhiyun /* Black/Digital Clamp configuration */ 412*4882a593Smuzhiyun struct isif_black_clamp bclamp; 413*4882a593Smuzhiyun /* Gain, offset adjustments */ 414*4882a593Smuzhiyun struct isif_gain_offsets_adj gain_offset; 415*4882a593Smuzhiyun /* Culling */ 416*4882a593Smuzhiyun struct isif_cul culling; 417*4882a593Smuzhiyun /* A-Law and DPCM compression options */ 418*4882a593Smuzhiyun struct isif_compress compress; 419*4882a593Smuzhiyun /* horizontal offset for Gain/LSC/DFC */ 420*4882a593Smuzhiyun __u16 horz_offset; 421*4882a593Smuzhiyun /* vertical offset for Gain/LSC/DFC */ 422*4882a593Smuzhiyun __u16 vert_offset; 423*4882a593Smuzhiyun /* color pattern for field 0 */ 424*4882a593Smuzhiyun struct isif_col_pat col_pat_field0; 425*4882a593Smuzhiyun /* color pattern for field 1 */ 426*4882a593Smuzhiyun struct isif_col_pat col_pat_field1; 427*4882a593Smuzhiyun #define ISIF_NO_SHIFT 0 428*4882a593Smuzhiyun #define ISIF_1BIT_SHIFT 1 429*4882a593Smuzhiyun #define ISIF_2BIT_SHIFT 2 430*4882a593Smuzhiyun #define ISIF_3BIT_SHIFT 3 431*4882a593Smuzhiyun #define ISIF_4BIT_SHIFT 4 432*4882a593Smuzhiyun #define ISIF_5BIT_SHIFT 5 433*4882a593Smuzhiyun #define ISIF_6BIT_SHIFT 6 434*4882a593Smuzhiyun /* Data shift applied before storing to SDRAM */ 435*4882a593Smuzhiyun __u8 data_shift; 436*4882a593Smuzhiyun /* enable input test pattern generation */ 437*4882a593Smuzhiyun __u8 test_pat_gen; 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun #ifdef __KERNEL__ 441*4882a593Smuzhiyun struct isif_ycbcr_config { 442*4882a593Smuzhiyun /* isif pixel format */ 443*4882a593Smuzhiyun enum ccdc_pixfmt pix_fmt; 444*4882a593Smuzhiyun /* isif frame format */ 445*4882a593Smuzhiyun enum ccdc_frmfmt frm_fmt; 446*4882a593Smuzhiyun /* ISIF crop window */ 447*4882a593Smuzhiyun struct v4l2_rect win; 448*4882a593Smuzhiyun /* field polarity */ 449*4882a593Smuzhiyun enum vpfe_pin_pol fid_pol; 450*4882a593Smuzhiyun /* interface VD polarity */ 451*4882a593Smuzhiyun enum vpfe_pin_pol vd_pol; 452*4882a593Smuzhiyun /* interface HD polarity */ 453*4882a593Smuzhiyun enum vpfe_pin_pol hd_pol; 454*4882a593Smuzhiyun /* isif pix order. Only used for ycbcr capture */ 455*4882a593Smuzhiyun enum ccdc_pixorder pix_order; 456*4882a593Smuzhiyun /* isif buffer type. Only used for ycbcr capture */ 457*4882a593Smuzhiyun enum ccdc_buftype buf_type; 458*4882a593Smuzhiyun }; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun /* MSB of image data connected to sensor port */ 461*4882a593Smuzhiyun enum isif_data_msb { 462*4882a593Smuzhiyun ISIF_BIT_MSB_15, 463*4882a593Smuzhiyun ISIF_BIT_MSB_14, 464*4882a593Smuzhiyun ISIF_BIT_MSB_13, 465*4882a593Smuzhiyun ISIF_BIT_MSB_12, 466*4882a593Smuzhiyun ISIF_BIT_MSB_11, 467*4882a593Smuzhiyun ISIF_BIT_MSB_10, 468*4882a593Smuzhiyun ISIF_BIT_MSB_9, 469*4882a593Smuzhiyun ISIF_BIT_MSB_8, 470*4882a593Smuzhiyun ISIF_BIT_MSB_7 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun enum isif_cfa_pattern { 474*4882a593Smuzhiyun ISIF_CFA_PAT_MOSAIC, 475*4882a593Smuzhiyun ISIF_CFA_PAT_STRIPE 476*4882a593Smuzhiyun }; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun struct isif_params_raw { 479*4882a593Smuzhiyun /* isif pixel format */ 480*4882a593Smuzhiyun enum ccdc_pixfmt pix_fmt; 481*4882a593Smuzhiyun /* isif frame format */ 482*4882a593Smuzhiyun enum ccdc_frmfmt frm_fmt; 483*4882a593Smuzhiyun /* video window */ 484*4882a593Smuzhiyun struct v4l2_rect win; 485*4882a593Smuzhiyun /* field polarity */ 486*4882a593Smuzhiyun enum vpfe_pin_pol fid_pol; 487*4882a593Smuzhiyun /* interface VD polarity */ 488*4882a593Smuzhiyun enum vpfe_pin_pol vd_pol; 489*4882a593Smuzhiyun /* interface HD polarity */ 490*4882a593Smuzhiyun enum vpfe_pin_pol hd_pol; 491*4882a593Smuzhiyun /* buffer type. Applicable for interlaced mode */ 492*4882a593Smuzhiyun enum ccdc_buftype buf_type; 493*4882a593Smuzhiyun /* Gain values */ 494*4882a593Smuzhiyun struct isif_gain gain; 495*4882a593Smuzhiyun /* cfa pattern */ 496*4882a593Smuzhiyun enum isif_cfa_pattern cfa_pat; 497*4882a593Smuzhiyun /* Data MSB position */ 498*4882a593Smuzhiyun enum isif_data_msb data_msb; 499*4882a593Smuzhiyun /* Enable horizontal flip */ 500*4882a593Smuzhiyun unsigned char horz_flip_en; 501*4882a593Smuzhiyun /* Enable image invert vertically */ 502*4882a593Smuzhiyun unsigned char image_invert_en; 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun /* all the userland defined stuff*/ 505*4882a593Smuzhiyun struct isif_config_params_raw config_params; 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun enum isif_data_pack { 509*4882a593Smuzhiyun ISIF_PACK_16BIT, 510*4882a593Smuzhiyun ISIF_PACK_12BIT, 511*4882a593Smuzhiyun ISIF_PACK_8BIT 512*4882a593Smuzhiyun }; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun #define ISIF_WIN_NTSC {0, 0, 720, 480} 515*4882a593Smuzhiyun #define ISIF_WIN_VGA {0, 0, 640, 480} 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun #endif 518*4882a593Smuzhiyun #endif 519